/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { #if DEBUG unsigned long mpidr = read_mpidr(); #endif /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); printf("BL31 %s\n\r", build_message); /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * Use the more complex exception vectors now that context * management is setup. SP_EL3 should point to a 'cpu_context' * structure which has an exception stack allocated. The PSCI * service should have set the context. */ assert(cm_get_context(mpidr, NON_SECURE)); cm_set_next_eret_context(NON_SECURE); cm_init_pcpu_ptr_cache(); write_vbar_el3((uint64_t) runtime_exceptions); isb(); next_image_type = NON_SECURE; /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. * If the SPD runtime service is present, it would want to pass control * to BL32 first in S-EL1. In that case, SPD would have registered a * function to intialize bl32 where it takes responsibility of entering * S-EL1 and returning control back to bl31_main. Once this is done we * can prepare entry into BL33 as normal. */ /* * If SPD had registerd an init hook, invoke it. Pass it the information * about memory extents */ if (bl32_init) (*bl32_init)(bl31_plat_get_bl32_mem_layout()); /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); }
/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { #if DEBUG unsigned long mpidr = read_mpidr(); #endif /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); #if defined (__GNUC__) printf("BL31 Built : %s, %s\n\r", __TIME__, __DATE__); #endif /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * Use the more complex exception vectors now that context * management is setup. SP_EL3 should point to a 'cpu_context' * structure which has an exception stack allocated. The PSCI * service should have set the context. */ assert(cm_get_context(mpidr, NON_SECURE)); cm_set_next_eret_context(NON_SECURE); write_vbar_el3((uint64_t) runtime_exceptions); /* * All the cold boot actions on the primary cpu are done. We * now need to decide which is the next image (BL32 or BL33) * and how to execute it. If the SPD runtime service is * present, it would want to pass control to BL32 first in * S-EL1. It will export the bl32_init() routine where it takes * responsibility of entering S-EL1 and returning control back * to bl31_main. Once this is done we can prepare entry into * BL33 as normal. */ /* Tell BL32 about it memory extents as well */ if (bl32_init) bl32_init(bl31_plat_get_bl32_mem_layout()); /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); }
__dead2 void tegra_soc_prepare_system_off(void) { mce_cstate_info_t cstate_info = { 0 }; uint32_t val; if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { /* power off the entire system */ mce_enter_ccplex_state(tegra186_system_powerdn_state); } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { /* Prepare for quasi power down */ cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; cstate_info.system = TEGRA_ARI_SYSTEM_SC8; cstate_info.system_state_force = 1; cstate_info.update_wake_mask = 1; mce_update_cstate_info(&cstate_info); /* loop until other CPUs power down */ do { val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); } while (val == 0); /* Enter quasi power down state */ (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); /* disable GICC */ tegra_gic_cpuif_deactivate(); /* power down core */ prepare_cpu_pwr_dwn(); /* flush L1/L2 data caches */ dcsw_op_all(DCCISW); } else { ERROR("%s: unsupported power down state (%d)\n", __func__, tegra186_system_powerdn_state); } wfi(); /* wait for the system to power down */ for (;;) { ; } }
/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader (UEFI) or Linux. This function calls * runtime_svc_init() which initializes all registered runtime services. The run * time services would setup enough context for the core to swtich to the next * exception level. When this function returns, the core will switch to the * programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { el_change_info *next_image_info; uint32_t scr; /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); #if defined (__GNUC__) printf("BL31 Built : %s, %s\n\r", __TIME__, __DATE__); #endif /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * Setup minimal architectural state of the next highest EL to * allow execution in it immediately upon entering it. */ bl31_arch_next_el_setup(); /* Program EL3 registers to enable entry into the next EL */ next_image_info = bl31_get_next_image_info(); scr = read_scr(); if (next_image_info->security_state == NON_SECURE) scr |= SCR_NS_BIT; /* * Tell the context mgmt. library to ensure that SP_EL3 points to * the right context to exit from EL3 correctly. */ cm_set_el3_eret_context(next_image_info->security_state, next_image_info->entrypoint, next_image_info->spsr, scr); /* Finally set the next context */ cm_set_next_eret_context(next_image_info->security_state); }
/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { NOTICE("BL3-1: %s\n", version_string); NOTICE("BL3-1: %s\n", build_message); /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ INFO("BL3-1: Initializing runtime services\n"); runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. * If the SPD runtime service is present, it would want to pass control * to BL32 first in S-EL1. In that case, SPD would have registered a * function to intialize bl32 where it takes responsibility of entering * S-EL1 and returning control back to bl31_main. Once this is done we * can prepare entry into BL33 as normal. */ /* * If SPD had registerd an init hook, invoke it. */ if (bl32_init) { INFO("BL3-1: Initializing BL3-2\n"); (*bl32_init)(); } /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); }
static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node) { int rc = PSCI_E_SUCCESS; unsigned int plat_state; /* Sanity check the cluster level */ assert(cluster_node->level == MPIDR_AFFLVL1); /* State management: Decrement the cluster reference count */ psci_set_state(cluster_node, PSCI_STATE_OFF); /* * Keep the physical state of this cluster handy to decide * what action needs to be taken */ plat_state = psci_get_phys_state(cluster_node); /* * Arch. Management. Flush all levels of caches to PoC if * the cluster is to be shutdown */ if (plat_state == PSCI_STATE_OFF) dcsw_op_all(DCCISW); /* * Plat. Management. Allow the platform to do its cluster * specific bookeeping e.g. turn off interconnect coherency, * program the power controller etc. */ if (psci_plat_pm_ops->affinst_off) rc = psci_plat_pm_ops->affinst_off(mpidr, cluster_node->level, plat_state); return rc; }
static int stm32mp1_ddr_setup(void) { struct ddr_info *priv = &ddr_priv_data; int ret; struct stm32mp1_ddr_config config; int node, len; uint32_t uret, idx; void *fdt; #define PARAM(x, y) \ { \ .name = x, \ .offset = offsetof(struct stm32mp1_ddr_config, y), \ .size = sizeof(config.y) / sizeof(uint32_t) \ } #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) const struct { const char *name; /* Name in DT */ const uint32_t offset; /* Offset in config struct */ const uint32_t size; /* Size of parameters */ } param[] = { CTL_PARAM(reg), CTL_PARAM(timing), CTL_PARAM(map), CTL_PARAM(perf), PHY_PARAM(reg), PHY_PARAM(timing), PHY_PARAM(cal) }; if (fdt_get_address(&fdt) == 0) { return -ENOENT; } node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); if (node < 0) { ERROR("%s: Cannot read DDR node in DT\n", __func__); return -EINVAL; } config.info.speed = fdt_read_uint32_default(node, "st,mem-speed", 0); if (!config.info.speed) { VERBOSE("%s: no st,mem-speed\n", __func__); return -EINVAL; } config.info.size = fdt_read_uint32_default(node, "st,mem-size", 0); if (!config.info.size) { VERBOSE("%s: no st,mem-size\n", __func__); return -EINVAL; } config.info.name = fdt_getprop(fdt, node, "st,mem-name", &len); if (config.info.name == NULL) { VERBOSE("%s: no st,mem-name\n", __func__); return -EINVAL; } INFO("RAM: %s\n", config.info.name); for (idx = 0; idx < ARRAY_SIZE(param); idx++) { ret = fdt_read_uint32_array(node, param[idx].name, (void *)((uintptr_t)&config + param[idx].offset), param[idx].size); VERBOSE("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); if (ret != 0) { ERROR("%s: Cannot read %s\n", __func__, param[idx].name); return -EINVAL; } } /* Disable axidcg clock gating during init */ mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); stm32mp1_ddr_init(priv, &config); /* Enable axidcg clock gating */ mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); priv->info.size = config.info.size; VERBOSE("%s : ram size(%x, %x)\n", __func__, (uint32_t)priv->info.base, (uint32_t)priv->info.size); write_sctlr(read_sctlr() & ~SCTLR_C_BIT); dcsw_op_all(DC_OP_CISW); uret = ddr_test_data_bus(); if (uret != 0U) { ERROR("DDR data bus test: can't access memory @ 0x%x\n", uret); panic(); } uret = ddr_test_addr_bus(); if (uret != 0U) { ERROR("DDR addr bus test: can't access memory @ 0x%x\n", uret); panic(); } uret = ddr_check_size(); if (uret < config.info.size) { ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", uret, config.info.size); panic(); } write_sctlr(read_sctlr() | SCTLR_C_BIT); return 0; }
/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { /* Show Only to UART */ NOTICE("BL3-1: %s\n", version_string); NOTICE("BL3-1: %s\n", build_message); atf_arg_t_ptr teearg = (atf_arg_t_ptr)(uintptr_t)TEE_BOOT_INFO_ADDR; /* Initialize for ATF log buffer */ if(teearg->atf_log_buf_size != 0) { teearg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE; teearg->atf_aee_debug_buf_start = teearg->atf_log_buf_start + teearg->atf_log_buf_size - ATF_AEE_BUFFER_SIZE; mt_log_setup(teearg->atf_log_buf_start, teearg->atf_log_buf_size, teearg->atf_aee_debug_buf_size); printf("ATF log service is registered (0x%x, aee:0x%x)\n", teearg->atf_log_buf_start, teearg->atf_aee_debug_buf_start); } else { teearg->atf_aee_debug_buf_size = 0; teearg->atf_aee_debug_buf_start = 0; } /* Show to ATF log buffer & UART */ printf("BL3-1: %s\n", version_string); printf("BL3-1: %s\n", build_message); /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ INFO("BL3-1: Initializing runtime services\n"); runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. * If the SPD runtime service is present, it would want to pass control * to BL32 first in S-EL1. In that case, SPD would have registered a * function to intialize bl32 where it takes responsibility of entering * S-EL1 and returning control back to bl31_main. Once this is done we * can prepare entry into BL33 as normal. */ /* * If SPD had registerd an init hook, invoke it. */ if(teearg->tee_support) { printf("[BL31] Jump to secure OS for initialization!\n\r"); if (bl32_init) { (*bl32_init)(); } else { printf("[ERROR] Secure OS is not initialized!\n\r"); } } else { printf("[BL31] Jump to FIQD for initialization!\n\r"); if (bl32_init) { (*bl32_init)(); } } /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); printf("[BL31] Final dump!\n\r"); clear_uart_flag(); printf("[BL31] SHOULD not dump in UART but in log buffer!\n\r"); }
/******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { #if DEBUG unsigned long mpidr = read_mpidr(); #endif atf_arg_t_ptr teearg = (atf_arg_t_ptr)(uintptr_t)TEE_BOOT_INFO_ADDR; if(teearg->atf_log_buf_size != 0) { teearg->atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE; teearg->atf_aee_debug_buf_start = teearg->atf_log_buf_start + teearg->atf_log_buf_size - ATF_AEE_BUFFER_SIZE; mt_log_setup(teearg->atf_log_buf_start, teearg->atf_log_buf_size, teearg->atf_aee_debug_buf_size); printf("ATF log service is registered (0x%x, aee:0x%x)\n", teearg->atf_log_buf_start, teearg->atf_aee_debug_buf_start); } else { teearg->atf_aee_debug_buf_size = 0; teearg->atf_aee_debug_buf_start = 0; } /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); printf("BL31 %s\n\r", build_message); /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * Use the more complex exception vectors now that context * management is setup. SP_EL3 should point to a 'cpu_context' * structure which has an exception stack allocated. The PSCI * service should have set the context. */ assert(cm_get_context(mpidr, NON_SECURE)); cm_set_next_eret_context(NON_SECURE); cm_init_pcpu_ptr_cache(); write_vbar_el3((uint64_t) runtime_exceptions); isb(); next_image_type = NON_SECURE; /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. * If the SPD runtime service is present, it would want to pass control * to BL32 first in S-EL1. In that case, SPD would have registered a * function to intialize bl32 where it takes responsibility of entering * S-EL1 and returning control back to bl31_main. Once this is done we * can prepare entry into BL33 as normal. */ /* * If SPD had registerd an init hook, invoke it. */ if(teearg->tee_support) { printf("[BL31] Jump to secure OS for initialization!\n\r"); if (bl32_init) { (*bl32_init)(teearg->tee_entry, teearg->tee_boot_arg_addr); } else { printf("[ERROR] Secure OS is not initialized!\n\r"); //assert(0); } } else { printf("[BL31] Jump to FIQD for initialization!\n\r"); if (bl32_init) { (*bl32_init)(0, 0); } } /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); printf("[BL31] Final dump!\n\r"); clear_uart_flag(); printf("[BL31] SHOULD not dump in UART but in log buffer!\n\r"); }