int ddp_remove_module(DDP_SCENARIO_ENUM ddp_scenario, DISP_MODULE_ENUM module)
{
int i = 0;
int idx = ddp_find_module_index(ddp_scenario,module);
if( idx < 0)
{
DDPERR("ddp_remove_module, can not find module %s in scenario %s\n", ddp_get_module_name(module), ddp_get_scenario_name(ddp_scenario));
return -1;
}
for(i=idx; i<DDP_ENING_NUM-1; i++)
{
module_list_scenario[ddp_scenario][i] = module_list_scenario[ddp_scenario][i+1];
}
module_list_scenario[ddp_scenario][DDP_ENING_NUM-1] = -1;
{
int * modules = ddp_get_scenario_list(ddp_scenario);
int module_num = ddp_get_module_num(ddp_scenario);
DDPMSG("after remove module, module list is: \n");
for(i=0;i<module_num;i++)
{
printk("%s-", ddp_get_module_name(modules[i]));
}
}
return 0;
}
static void ddp_disconnect_path_l(int *module_list,void * handle)
{
unsigned int i, j, k;
int step = 0;
unsigned int mout = 0;
unsigned int reg_mout = 0;
unsigned int mout_idx = 0;
unsigned int module_num = ddp_get_module_num_l(module_list);
DDPDBG("disconnect_path: %s to %s\n",ddp_get_module_name(module_list[0]),
ddp_get_module_name(module_list[module_num-1]));
for(i = 0 ; i < module_num - 1 ; i++)
{
for(j = 0 ; j < DDP_MOUT_NUM ; j++)
{
if(module_list[i] == mout_map[j].id)
{
//find next module which can be connected
step = i+1;
while(module_can_connect[module_list[step]].bit==0 && step<module_num)
{
step++;
}
ASSERT(step<module_num);
for(k = 0 ; k < 5 ; k++)
{
if(mout_map[j].out_id_bit_map[k].m == -1)
break;
if(mout_map[j].out_id_bit_map[k].m == module_list[step])
{
mout |= mout_map[j].out_id_bit_map[k].v;
reg_mout |= mout;
mout_idx = j;
DDPDBG("disconnect mout %s to %s \n", ddp_get_module_name(module_list[i]),
ddp_get_module_name(module_list[step]));
break;
}
}
//update mout_value
mout_map[j].reg_val &= ~mout;
mout = 0;
}
}
if(reg_mout)
{
DISP_REG_SET(handle,mout_map[mout_idx].reg, mout_map[mout_idx].reg_val);
reg_mout = 0;
mout_idx = 0;
}
}
}
static int _build_path_rdma_dpi(void)
{
int ret = 0;
DISP_MODULE_ENUM dst_module = 0;
pgc->mode = EXTD_RDMA_DPI_MODE;
pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
if(pgc->dpmgr_handle)
{
EXT_DISP_LOG("dpmgr create path SUCCESS(%p)\n", pgc->dpmgr_handle);
}
else
{
EXT_DISP_LOG("dpmgr create path FAIL\n");
return -1;
}
dst_module = _get_dst_module_by_lcm(pgc->plcm);
dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
EXT_DISP_LOG("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
{
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_DISP_RDMA1;
sPort.Virtuality = ext_disp_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
if(ret == 0)
{
EXT_DISP_LOG("config M4U Port %s to %s SUCCESS\n",ddp_get_module_name(DISP_MODULE_RDMA1), ext_disp_use_m4u?"virtual":"physical");
}
else
{
EXT_DISP_LOG("config M4U Port %s to %s FAIL(ret=%d)\n",ddp_get_module_name(DISP_MODULE_RDMA1), ext_disp_use_m4u?"virtual":"physical", ret);
return -1;
}
}
dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
return ret;
}
int dpmgr_path_is_busy(disp_path_handle dp_handle)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_V("path check busy on scenario %s\n",ddp_get_scenario_name(handle->scenario));
for( i=module_num-1; i>=0;i--)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->is_busy!= 0)
{
if(ddp_modules_driver[module_name]->is_busy(module_name))
{
DISP_LOG_V("%s is busy\n", ddp_get_module_name(module_name));
return 1;
}
}
}
}
return 0;
}
int dpmgr_path_power_on(disp_path_handle dp_handle, CMDQ_SWITCH encmdq)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_I("path power on scenario %s\n",ddp_get_scenario_name(handle->scenario));
path_top_clock_on();
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->power_on!= 0)
{
DISP_LOG_I("%s power on\n",ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->power_on(module_name, encmdq?handle->cmdqhandle:NULL); // now just 0;
}
}
}
//modules on this path will resume power on;
handle->power_sate = 1;
return 0;
}
int dpmgr_path_trigger(disp_path_handle dp_handle, void *trigger_loop_handle, int encmdq)
{
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
DISP_LOG_V("dpmgr_path_trigger on scenario %s\n",ddp_get_scenario_name(handle->scenario));
cmdqRecHandle cmdqHandle = encmdq ? handle->cmdqhandle : NULL;
int i=0;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
int module_name ;
ddp_mutex_enable(handle->hwmutexid,handle->scenario,trigger_loop_handle);
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->trigger!= 0)
{
DISP_LOG_V("%s trigger\n",ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->trigger(module_name, trigger_loop_handle);
}
}
}
return 0;
}
int dpmgr_path_config(disp_path_handle dp_handle, disp_ddp_path_config * config, void * cmdq_handle)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_V("path config ovl %d, rdma %d, wdma %d, dst %d on handle 0x%x scenario %s \n",
config->ovl_dirty,
config->rdma_dirty,
config->wdma_dirty,
config->dst_dirty,
handle,
ddp_get_scenario_name(handle->scenario));
memcpy(&handle->last_config, config, sizeof(disp_ddp_path_config));
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->config!= 0)
{
DISP_LOG_V("scenario %s config module %s \n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->config(module_name, config, cmdq_handle);
}
}
}
return 0;
}
int dpmgr_path_reset(disp_path_handle dp_handle, int encmdq)
{
int i=0;
int ret = 0;
int error = 0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
cmdqRecHandle cmdqHandle = encmdq ? handle->cmdqhandle : NULL;
DISP_LOG_I("path reset on scenario %s\n",ddp_get_scenario_name(handle->scenario));
/* first reset mutex */
ddp_mutex_reset(handle->hwmutexid,cmdqHandle);
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->reset != 0)
{
DISP_LOG_I("scenario %s reset module %s \n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ret = ddp_modules_driver[module_name]->reset(module_name, cmdqHandle);
if(ret != 0)
{
error++;
}
}
}
}
return error > 0? -1: 0;
}
int dpmgr_path_ioctl(disp_path_handle dp_handle, void * cmdq_handle, DDP_IOCTL_NAME ioctl_cmd, unsigned long *params)
{
int i=0;
int ret = 0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_I("path IOCTL on scenario %s\n",ddp_get_scenario_name(handle->scenario));
for( i=module_num-1; i >= 0 ;i--)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->ioctl!= 0)
{
printk("scenario %s, module %s ioctl\n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ret += ddp_modules_driver[module_name]->ioctl(module_name, cmdq_handle, (unsigned int)ioctl_cmd, params);
}
}
}
return ret;
}
int dpmgr_path_stop(disp_path_handle dp_handle, int encmdq)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
cmdqRecHandle cmdqHandle = encmdq ? handle->cmdqhandle : NULL;
DISP_LOG_V("path stop on scenario %s\n",ddp_get_scenario_name(handle->scenario));
for( i=module_num-1; i>=0;i--)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->stop!= 0)
{
DISP_LOG_V("scenario %s stop module %s \n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->stop(module_name, cmdqHandle);
}
}
}
return 0;
}
int dpmgr_path_deinit(disp_path_handle dp_handle, int encmdq)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
cmdqRecHandle cmdqHandle = encmdq ? handle->cmdqhandle : NULL;
DISP_LOG_I("path deinit on scenario %s\n",ddp_get_scenario_name(handle->scenario));
ddp_mutex_Interrupt_disable(handle->hwmutexid,cmdqHandle);
ddp_mutex_clear(handle->hwmutexid,cmdqHandle);
ddp_disconnect_path(handle->scenario, cmdqHandle);
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->deinit!= 0)
{
DISP_LOG_I("scenario %s deinit module %s\n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->deinit(module_name, cmdqHandle);
}
if(ddp_modules_driver[module_name]->set_listener!= 0)
{
ddp_modules_driver[module_name]->set_listener(module_name,NULL);
}
}
}
handle->power_sate = 0;
//close top clock when last path init
path_top_clock_off();
return 0;
}
int dpmgr_path_set_dst_module(disp_path_handle dp_handle,DISP_MODULE_ENUM dst_module)
{
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
ASSERT((handle->scenario >= 0 && handle->scenario < DDP_SCENARIO_MAX));
DISP_LOG_I("set dst module on scenario %s, module %s\n",
ddp_get_scenario_name(handle->scenario),ddp_get_module_name(dst_module));
return ddp_set_dst_module(handle->scenario, dst_module);
}
static int ddp_mutex_set_l(int mutex_id, int* module_list, DDP_MODE ddp_mode, void * handle)
{
int i=0;
kal_uint32 value = 0;
int module_num = ddp_get_module_num_l(module_list);
MUTEX_SOF mode = ddp_get_mutex_sof(module_list[module_num-1],ddp_mode);
if(mutex_id < DISP_MUTEX_DDP_FIRST || mutex_id > DISP_MUTEX_DDP_LAST)
{
DDPERR("exceed mutex max (0 ~ %d)\n",DISP_MUTEX_DDP_LAST);
return -1;
}
for(i = 0 ; i < module_num ; i++)
{
if(module_mutex_map[module_list[i]].bit != -1)
{
DDPDBG("module %s added to mutex %d\n",ddp_get_module_name(module_list[i]),mutex_id);
value |= (1 << module_mutex_map[module_list[i]].bit);
}
else
{
DDPDBG("module %s not added to mutex %d\n",ddp_get_module_name(module_list[i]),mutex_id);
}
}
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),value);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(mutex_id),mode);
// for primary config thread, save more time for register config
if(gEnableMutexRisingEdge==1 && primary_display_is_video_mode()==1 && mutex_id==0)
{
DISP_REG_SET_FIELD(handle, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 1);
}
if(gEnableSWTrigger==1 && primary_display_is_video_mode()==1 && mutex_id==0)
{
// set OVL0/OVL1 to separate mutex
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(DISP_OVL_SEPARATE_MUTEX_ID),value&((1 << module_mutex_map[DISP_MODULE_OVL0].bit)|(1 << module_mutex_map[DISP_MODULE_OVL1].bit)));
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(DISP_OVL_SEPARATE_MUTEX_ID), SOF_SINGLE);
// move OVL0/OVL1 out from primary path
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),value&(~((1 << module_mutex_map[DISP_MODULE_OVL0].bit)|(1 << module_mutex_map[DISP_MODULE_OVL1].bit))));
}
DDPDBG("mutex %d value=0x%x, sof=%s\n",mutex_id, value, ddp_get_mutex_sof_name(mode));
return 0;
}
static void ddp_print_scenario(DDP_SCENARIO_ENUM scenario)
{
int i =0;
char path[512]={'\0'};
int num = ddp_get_module_num(scenario);
for(i=0; i< num; i++)
{
strcat(path,ddp_get_module_name(module_list_scenario[scenario][i]));
}
DDPMSG("scenario %s have modules: %s\n",ddp_get_scenario_name(scenario),path);
}
int ddp_insert_module(DDP_SCENARIO_ENUM ddp_scenario, DISP_MODULE_ENUM place, DISP_MODULE_ENUM module)
{
int i = DDP_ENING_NUM-1;
int idx = ddp_find_module_index(ddp_scenario,place);
if( idx < 0)
{
DDPERR("error: ddp_insert_module , place=%s is not in scenario %s!\n", ddp_get_module_name(place), ddp_get_scenario_name(ddp_scenario));
return -1;
}
for(i=0; i<DDP_ENING_NUM; i++)
{
if(module_list_scenario[ddp_scenario][i]==module)
{
//DDPERR("error: ddp_insert_module , module=%s is already in scenario %s!\n", ddp_get_module_name(module), ddp_get_scenario_name(ddp_scenario));
return -1;
}
}
//should have empty room for insert
ASSERT(module_list_scenario[ddp_scenario][DDP_ENING_NUM-1] == -1);
for(i=DDP_ENING_NUM-2; i>=idx; i--)
{
module_list_scenario[ddp_scenario][i+1] = module_list_scenario[ddp_scenario][i];
}
module_list_scenario[ddp_scenario][idx] = module;
if(0)
{
int * modules = ddp_get_scenario_list(ddp_scenario);
int module_num = ddp_get_module_num(ddp_scenario);
DDPMSG("after insert module, module list is: \n");
for(i=0;i<module_num;i++)
{
printk("%s-", ddp_get_module_name(modules[i]));
}
}
return 0;
}
int ddp_mutex_add_module(int mutex_id, DISP_MODULE_ENUM module, void * handle)
{
int value = 0;
if (module < DISP_MODULE_UNKNOWN ){
if (module_mutex_map[module].bit != -1){
DDPDBG("module %s added to mutex %d\n",ddp_get_module_name(module),mutex_id);
value |= (1 << module_mutex_map[module].bit);
DISP_REG_MASK(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id), value, value);
}
}
return 0;
}
// set display interface when kernel init
int ddp_set_dst_module(DDP_SCENARIO_ENUM scenario, DISP_MODULE_ENUM dst_module)
{
int i = 0;
DDPMSG("ddp_set_dst_module, scenario=%s, dst_module=%s \n",
ddp_get_scenario_name(scenario), ddp_get_module_name(dst_module));
if (ddp_find_module_index(scenario,dst_module) > 0) {
DDPDBG("%s is already on path\n",ddp_get_module_name(dst_module));
return 0;
}
i = ddp_get_module_num_l(module_list_scenario[scenario])-1;
ASSERT(i>=0);
if (dst_module == DISP_MODULE_DSIDUAL) {
if (i < (DDP_ENING_NUM -1)) {
module_list_scenario[scenario][i++] = DISP_MODULE_SPLIT1;
}else{
DDPERR("set dst module over up bound\n");
return -1;
}
}
else
{
if(ddp_get_dst_module(scenario)==DISP_MODULE_DSIDUAL)
{
if (i >= 1) {
module_list_scenario[scenario][i--] = -1;
}else{
DDPERR("set dst module over low bound\n");
return -1;
}
}
}
module_list_scenario[scenario][i] = dst_module;
if (scenario == DDP_SCENARIO_PRIMARY_ALL) {
ddp_set_dst_module(DDP_SCENARIO_PRIMARY_DISP,dst_module);
}else if(scenario==DDP_SCENARIO_SUB_ALL) {
ddp_set_dst_module(DDP_SCENARIO_SUB_DISP,dst_module);
}
ddp_print_scenario(scenario);
return 0;
}
DISP_MODULE_ENUM ddp_get_dst_module(DDP_SCENARIO_ENUM ddp_scenario)
{
DISP_MODULE_ENUM module_name = DISP_MODULE_UNKNOWN;
int module_num = ddp_get_module_num_l(module_list_scenario[ddp_scenario])-1;
if(module_num >=0 )
module_name = module_list_scenario[ddp_scenario][module_num];
DDPMSG("ddp_get_dst_module, scneario=%s, dst_module=%s\n",
ddp_get_scenario_name(ddp_scenario),
ddp_get_module_name(module_name));
return module_name;
}
static int ddp_find_module_index(DDP_SCENARIO_ENUM ddp_scenario, DISP_MODULE_ENUM module)
{
int i=0;
for(i=0; i< DDP_ENING_NUM; i++)
{
if(module_list_scenario[ddp_scenario][i] == module)
{
return i;
}
}
DDPDBG("find module: can not find module %s on scenario %s\n",ddp_get_module_name(module),
ddp_get_scenario_name(ddp_scenario));
return -1;
}
static MUTEX_SOF ddp_get_mutex_sof(DISP_MODULE_ENUM dest_module, DDP_MODE ddp_mode)
{
MUTEX_SOF mode = SOF_SINGLE;
switch(dest_module)
{
case DISP_MODULE_DSI0:
{
mode = (ddp_mode==DDP_VIDEO_MODE ? SOF_DSI0 : SOF_SINGLE);
break;
}
case DISP_MODULE_DSI1:
{
mode = (ddp_mode==DDP_VIDEO_MODE ? SOF_DSI1 : SOF_SINGLE);
break;
}
case DISP_MODULE_DSIDUAL:
{
mode = (ddp_mode==DDP_VIDEO_MODE ? SOF_DSI0 : SOF_SINGLE);
break;
}
case DISP_MODULE_DPI:
{
mode = SOF_DSI1;//SOF_DPI0; has one DSI, so the DPI should use 1 for mutex_sof
break;
}
case DISP_MODULE_WDMA0:
case DISP_MODULE_WDMA1:
mode = SOF_SINGLE;
break;
default:
DDPERR("get mutex sof, invalid param dst module = %s(%d), dis mode %s\n",
ddp_get_module_name(dest_module), dest_module,ddp_get_mode_name(ddp_mode));
}
DDPDBG("mutex sof: %s dst module %s:%s\n",
ddp_get_mutex_sof_name(mode), ddp_get_module_name(dest_module),ddp_get_mode_name(ddp_mode));
return mode;
}
int dpmgr_path_init(disp_path_handle dp_handle, int encmdq)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
cmdqRecHandle cmdqHandle = encmdq ? handle->cmdqhandle : NULL;
DISP_LOG_I("path init on scenario %s\n",ddp_get_scenario_name(handle->scenario));
//open top clock
path_top_clock_on();
//seting mutex
ddp_mutex_set(handle->hwmutexid, handle->scenario, handle->mode, cmdqHandle);
if(handle->hwmutexid != 0)
{
ddp_mutex_Interrupt_enable(handle->hwmutexid, cmdqHandle);
}
//connect path;
ddp_connect_path(handle->scenario,cmdqHandle);
// each module init
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->init!= 0)
{
DISP_LOG_I("scenario %s init module %s\n",ddp_get_scenario_name(handle->scenario),
ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->init(module_name, cmdqHandle);
}
if(ddp_modules_driver[module_name]->set_listener!= 0)
{
ddp_modules_driver[module_name]->set_listener(module_name,dpmgr_module_notify);
}
}
}
//after init this path will power on;
handle->power_sate = 1;
return 0;
}
// id: mutex ID, 0~5
static int ddp_mutex_set_l(int mutex_id, int* module_list, DDP_MODE ddp_mode, void * handle)
{
int i=0;
kal_uint32 value = 0;
int module_num = ddp_get_module_num_l(module_list);
MUTEX_SOF mode = ddp_get_mutex_sof(module_list[module_num-1],ddp_mode);
if(mutex_id < DISP_MUTEX_DDP_FIRST || mutex_id > DISP_MUTEX_DDP_LAST)
{
DDPERR("exceed mutex max (0 ~ %d)\n",DISP_MUTEX_DDP_LAST);
return -1;
}
for(i = 0 ; i < module_num ; i++)
{
if(module_mutex_map[module_list[i]].bit != -1)
DDPDBG("module %s added to mutex %d\n",ddp_get_module_name(module_list[i]),mutex_id);
value |= (1 << module_mutex_map[module_list[i]].bit);
}
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),value);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(mutex_id),mode);
DDPDBG("mutex %d value=0x%x, sof=%s\n",mutex_id, value, ddp_get_mutex_sof_name(mode));
return 0;
}
int dpmgr_set_lcm_utils(disp_path_handle dp_handle, void *lcm_drv)
{
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_V("path set lcm drv handle 0x%x\n",handle);
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if((ddp_modules_driver[module_name]->set_lcm_utils!= 0)&&lcm_drv)
{
DISP_LOG_I("%s set lcm utils\n",ddp_get_module_name(module_name));
ddp_modules_driver[module_name]->set_lcm_utils(module_name, lcm_drv); // now just 0;
}
}
}
return 0;
}
int dpmgr_path_build_cmdq(disp_path_handle dp_handle, void *trigger_loop_handle, CMDQ_STATE state)
{
int ret = 0;
int i=0;
int module_name ;
ASSERT(dp_handle != NULL);
ddp_path_handle handle = (ddp_path_handle)dp_handle;
int * modules = ddp_get_scenario_list(handle->scenario);
int module_num = ddp_get_module_num(handle->scenario);
DISP_LOG_D("path build cmdq on scenario %s\n",ddp_get_scenario_name(handle->scenario));
for( i=0; i< module_num;i++)
{
module_name = modules[i];
if(ddp_modules_driver[module_name] != 0)
{
if(ddp_modules_driver[module_name]->build_cmdq!= 0)
{
DISP_LOG_D("%s build cmdq, state=%d\n",ddp_get_module_name(module_name), state);
ret = ddp_modules_driver[module_name]->build_cmdq(module_name, trigger_loop_handle, state); // now just 0;
}
}
}
return ret;
}
// config mout/msel to creat a compelte path
static void ddp_connect_path_l(int *module_list, void * handle)
{
unsigned int i, j, k;
int step=0;
unsigned int mout=0;
unsigned int reg_mout = 0;
unsigned int mout_idx = 0;
unsigned int module_num = ddp_get_module_num_l(module_list);
DDPDBG("connect_path: %s to %s\n",ddp_get_module_name(module_list[0]),
ddp_get_module_name(module_list[module_num-1]));
// connect mout
for(i = 0 ; i < module_num - 1 ; i++)
{
for(j = 0 ; j < DDP_MOUT_NUM ; j++)
{
if(module_list[i] == mout_map[j].id)
{
//find next module which can be connected
step = i+1;
while(module_can_connect[module_list[step]].bit==0 && step<module_num)
{
step++;
}
ASSERT(step<module_num);
mout = mout_map[j].reg_val;
for(k = 0 ; k < 5 ; k++)
{
if(mout_map[j].out_id_bit_map[k].m == -1)
break;
if(mout_map[j].out_id_bit_map[k].m == module_list[step])
{
mout |= mout_map[j].out_id_bit_map[k].v;
reg_mout |= mout;
mout_idx = j;
DDPDBG("connect mout %s to %s value 0x%x\n", ddp_get_module_name(module_list[i]),
ddp_get_module_name(module_list[step]),reg_mout);
break;
}
}
mout_map[j].reg_val = mout;
mout = 0;
}
}
if(reg_mout)
{
DISP_REG_SET(handle,mout_map[mout_idx].reg, reg_mout);
reg_mout = 0;
mout_idx = 0;
}
}
// connect out select
for(i = 0 ; i < module_num - 1 ; i++)
{
for(j = 0 ; j < DDP_SEL_OUT_NUM ; j++)
{
if(module_list[i] == sel_out_map[j].id)
{
step = i+1;
//find next module which can be connected
while(module_can_connect[module_list[step]].bit==0 && step<module_num)
{
step++;
}
ASSERT(step<module_num);
for(k = 0 ; k < 4 ; k++)
{
if(sel_out_map[j].id_bit_map[k] == -1)
break;
if(sel_out_map[j].id_bit_map[k] == module_list[step])
{
DDPDBG("connect out_s %s to %s, bits=0x%x\n", ddp_get_module_name(module_list[i]),
ddp_get_module_name(module_list[step]), k);
DISP_REG_SET(handle,sel_out_map[j].reg, (kal_uint16)k);
break;
}
}
}
}
}
// connect input select
for(i = 1 ; i < module_num ; i++)
{
for(j = 0 ; j < DDP_SEL_IN_NUM ; j++)
{
if(module_list[i] == sel_in_map[j].id)
{
step = i-1;
//find next module which can be connected
while(module_can_connect[module_list[step]].bit==0 && step>0)
{
step--;
}
ASSERT(step>=0);
for(k = 0 ; k < 4 ; k++)
{
if(sel_in_map[j].id_bit_map[k] == -1)
break;
if(sel_in_map[j].id_bit_map[k] == module_list[step])
{
DDPDBG("connect in_s %s to %s, bits=0x%x\n", ddp_get_module_name(module_list[step]),
ddp_get_module_name(module_list[i]), k);
DISP_REG_SET(handle,sel_in_map[j].reg, (kal_uint16)k);
break;
}
}
}
}
}
}
static void ddp_check_path_l(int *module_list)
{
unsigned int i, j, k;
int step = 0;
int valid =0;
unsigned int mout;
unsigned int path_error = 0;
unsigned int module_num = ddp_get_module_num_l(module_list);
DDPDUMP("check_path: %s to %s\n",ddp_get_module_name(module_list[0])
,ddp_get_module_name(module_list[module_num-1]));
// check mout
for(i = 0 ; i < module_num - 1 ; i++)
{
for(j = 0 ; j < DDP_MOUT_NUM ; j++)
{
if(module_list[i] == mout_map[j].id)
{
mout = 0;
//find next module which can be connected
step = i+1;
while(module_can_connect[module_list[step]].bit==0 && step<module_num)
{
step++;
}
ASSERT(step<module_num);
for(k = 0 ; k < 5 ; k++)
{
if(mout_map[j].out_id_bit_map[k].m == -1)
break;
if(mout_map[j].out_id_bit_map[k].m == module_list[step])
{
mout |= mout_map[j].out_id_bit_map[k].v;
valid =1;
break;
}
}
if(valid)
{
valid =0;
if((DISP_REG_GET(mout_map[j].reg) & mout)==0)
{
path_error += 1;
DDPDUMP("error:%s mout, expect=0x%x, real=0x%x \n",
ddp_get_module_name(module_list[i]),
mout,
DISP_REG_GET(mout_map[j].reg));
}
else if(DISP_REG_GET(mout_map[j].reg) != mout)
{
DDPDUMP("warning: %s mout expect=0x%x, real=0x%x \n",
ddp_get_module_name(module_list[i]),
mout,
DISP_REG_GET(mout_map[j].reg));
}
}
break;
}
}
}
// check out select
for(i = 0 ; i < module_num - 1 ; i++)
{
for(j = 0 ; j < DDP_SEL_OUT_NUM ; j++)
{
if(module_list[i] == sel_out_map[j].id)
{
//find next module which can be connected
step = i+1;
while(module_can_connect[module_list[step]].bit==0 && step<module_num)
{
step++;
}
ASSERT(step<module_num);
for(k = 0 ; k < 4 ; k++)
{
if(sel_out_map[j].id_bit_map[k] == -1)
break;
if(sel_out_map[j].id_bit_map[k] == module_list[step])
{
if(DISP_REG_GET(sel_out_map[j].reg) != k)
{
path_error += 1;
DDPDUMP("error:out_s %s not connect to %s, expect=0x%x, real=0x%x \n",
ddp_get_module_name(module_list[i]),ddp_get_module_name(module_list[step]),
k,
DISP_REG_GET(sel_out_map[j].reg));
}
break;
}
}
}
}
}
// check input select
for(i = 1 ; i < module_num ; i++)
{
for(j = 0 ; j < DDP_SEL_IN_NUM ; j++)
{
if(module_list[i] == sel_in_map[j].id)
{
//find next module which can be connected
step = i-1;
while(module_can_connect[module_list[step]].bit==0 && step>0)
{
step--;
}
ASSERT(step>=0);
for(k = 0 ; k < 4 ; k++)
{
if(sel_in_map[j].id_bit_map[k] == -1)
break;
if(sel_in_map[j].id_bit_map[k] == module_list[step])
{
if(DISP_REG_GET(sel_in_map[j].reg) != k)
{
path_error += 1;
DDPDUMP("error:in_s %s not connect to %s, expect=0x%x, real=0x%x \n",
ddp_get_module_name(module_list[step]),ddp_get_module_name(module_list[i]),
k,
DISP_REG_GET(sel_in_map[j].reg));
}
break;
}
}
}
}
}
if(path_error == 0)
{
DDPDUMP("path: %s to %s is connected\n",ddp_get_module_name(module_list[0]),
ddp_get_module_name(module_list[module_num - 1]));
}
else
{
DDPDUMP("path: %s to %s not connected!!!\n",ddp_get_module_name(module_list[0]),
ddp_get_module_name(module_list[module_num - 1]));
}
}
int ovl2mem_init(unsigned int session)
{
int ret = -1;
DISPFUNC();
dpmgr_init();
mutex_init(&(pgc->lock));
_ovl2mem_path_lock(__func__);
if(pgc->state > 0)
goto Exit;
#if 0
ret = cmdqCoreRegisterCB(CMDQ_GROUP_DISP, cmdqDdpClockOn,cmdqDdpDumpInfo,cmdqDdpResetEng,cmdqDdpClockOff);
if(ret)
{
DISPERR("cmdqCoreRegisterCB failed, ret=%d \n", ret);
goto done;
}
#endif
ret = cmdqRecCreate(CMDQ_SCENARIO_SUB_DISP,&(pgc->cmdq_handle_config));
if(ret)
{
DISPCHECK("cmdqRecCreate FAIL, ret=%d \n", ret);
goto Exit;
}
else
{
DISPCHECK("cmdqRecCreate SUCCESS, cmdq_handle=%p\n", pgc->cmdq_handle_config);
}
pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_OVL_MEMOUT, pgc->cmdq_handle_config);
if(pgc->dpmgr_handle)
{
DISPCHECK("dpmgr create path SUCCESS(%p)\n", pgc->dpmgr_handle);
}
else
{
DISPCHECK("dpmgr create path FAIL\n");
goto Exit;
}
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_DISP_OVL1;
sPort.Virtuality = ovl2mem_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
sPort.ePortID = M4U_PORT_DISP_WDMA1;
sPort.Virtuality = ovl2mem_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
if(ret == 0)
{
DISPCHECK("config M4U Port %s to %s SUCCESS\n",ddp_get_module_name(DISP_MODULE_OVL1), ovl2mem_use_m4u?"virtual":"physical");
}
else
{
DISPCHECK("config M4U Port %s to %s FAIL(ret=%d)\n",ddp_get_module_name(DISP_MODULE_OVL1), ovl2mem_use_m4u?"virtual":"physical", ret);
goto Exit;
}
dpmgr_path_set_video_mode(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
dpmgr_path_reset(pgc->dpmgr_handle, CMDQ_DISABLE);
//dpmgr_path_set_dst_module(pgc->dpmgr_handle,DISP_MODULE_ENUM dst_module)
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_COMPLETE);
pgc->max_layer = 4;
pgc->state = 1;
pgc->session = session;
atomic_set(&g_trigger_ticket, 1);
atomic_set(&g_release_ticket, 1);
Exit:
_ovl2mem_path_unlock(__func__);
DISPMSG("ovl2mem_init done\n");
return ret;
}
static int wdma_config(DISP_MODULE_ENUM module,
unsigned srcWidth,
unsigned srcHeight,
unsigned clipX,
unsigned clipY,
unsigned clipWidth,
unsigned clipHeight,
DpColorFormat out_format,
unsigned long dstAddress,
unsigned dstPitch,
unsigned int useSpecifiedAlpha,
unsigned char alpha,
DISP_BUFFER_TYPE sec,
void * handle)
{
unsigned int idx = wdma_index(module);
unsigned int output_swap = fmt_swap(out_format);
unsigned int output_color_space = fmt_color_space(out_format);
unsigned int out_fmt_reg = fmt_hw_value(out_format);
unsigned int yuv444_to_yuv422 = 0;
int color_matrix = 0x2; //0010 RGB_TO_BT601
unsigned int idx_offst = idx*DISP_WDMA_INDEX_OFFSET;
size_t size = dstPitch * clipHeight;
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("module %s, src(w=%d,h=%d), clip(x=%d,y=%d,w=%d,h=%d),out_fmt=%s,dst_address=0x%lx,dst_p=%d,spific_alfa=%d,alpa=%d,handle=0x%p,sec%d\n",
ddp_get_module_name(module),srcWidth,srcHeight,
clipX,clipY,clipWidth,clipHeight,
fmt_string(out_format),dstAddress,dstPitch,
useSpecifiedAlpha,alpha,handle,sec);
#endif
// should use OVL alpha instead of sw config
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_SRC_SIZE, srcHeight<<16 | srcWidth);
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_CLIP_COORD, clipY<<16 | clipX);
DISP_REG_SET(handle,idx_offst+DISP_REG_WDMA_CLIP_SIZE, clipHeight<<16 | clipWidth);
DISP_REG_SET_FIELD(handle,CFG_FLD_OUT_FORMAT,idx_offst+DISP_REG_WDMA_CFG, out_fmt_reg);
if(output_color_space == WDMA_COLOR_SPACE_YUV) {
yuv444_to_yuv422 = fmt_is_yuv422(out_format);
// set DNSP for UYVY and YUV_3P format for better quality
DISP_REG_SET_FIELD(handle,CFG_FLD_DNSP_SEL, idx_offst+DISP_REG_WDMA_CFG, yuv444_to_yuv422);
if(fmt_is_yuv420(out_format))
{
wdma_config_yuv420(module,out_format,dstPitch,clipHeight,dstAddress,sec,handle);
}
/*user internal matrix*/
DISP_REG_SET_FIELD(handle,CFG_FLD_EXT_MTX_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
DISP_REG_SET_FIELD(handle,CFG_FLD_CT_EN, idx_offst+DISP_REG_WDMA_CFG, 1);
DISP_REG_SET_FIELD(handle,CFG_FLD_INT_MTX_SEL, idx_offst+DISP_REG_WDMA_CFG, color_matrix);
}
else
{
DISP_REG_SET_FIELD(handle,CFG_FLD_EXT_MTX_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
DISP_REG_SET_FIELD(handle,CFG_FLD_CT_EN, idx_offst+DISP_REG_WDMA_CFG, 0);
}
DISP_REG_SET_FIELD(handle,CFG_FLD_SWAP, idx_offst+DISP_REG_WDMA_CFG, output_swap);
if(sec != DISP_SECURE_BUFFER) {
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_DST_ADDR0, dstAddress);
} else {
int m4u_port;
m4u_port = M4U_PORT_DISP_WDMA0;
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
cmdqRecWriteSecure(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_DST_ADDR0),
CMDQ_SAM_H_2_MVA, dstAddress, 0, size, m4u_port);
}
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_DST_W_IN_BYTE, dstPitch);
DISP_REG_SET_FIELD(handle,ALPHA_FLD_A_SEL, idx_offst+DISP_REG_WDMA_ALPHA, useSpecifiedAlpha);
DISP_REG_SET_FIELD(handle,ALPHA_FLD_A_VALUE, idx_offst+DISP_REG_WDMA_ALPHA, alpha);
wdma_calc_ultra(idx, srcWidth, srcHeight, 6, 60, handle);
return 0;
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
static disp_session_config config;
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);
if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U)
{
unsigned int regVal = DISP_REG_GET(addr);
DDPMSG("regr: 0x%lx = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%lx = 0x%08X\n", addr, regVal);
} else {
sprintf(buf, "regr, invalid address 0x%lx\n", addr);
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U)
{
unsigned int regVal;
DISP_CPU_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DDPMSG("regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
sprintf(buf, "regw, invalid address 0x%lx \n", addr);
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log_level = 1;
else
dbg_log_level = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log_level);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log_level = 1;
else
irq_log_level = 0;
sprintf(buf, "irq_log: %d\n", irq_log_level);
}
else if (0 == strncmp(opt, "met_on:", 7))
{
char *p = (char *)opt + 7;
int met_on = (int) simple_strtoul(p, &p, 10);
int rdma0_mode = (int) simple_strtoul(p + 1, &p, 10);
int rdma1_mode = (int) simple_strtoul(p + 1, &p, 10);
// ddp_init_met_tag(met_on,rdma0_mode,rdma1_mode);
DDPMSG("process_dbg_opt, met_on=%d,rdma0_mode %d, rdma1 %d \n", met_on,rdma0_mode,rdma1_mode);
sprintf(buf, "met_on:%d,rdma0_mode:%d,rdma1_mode:%d\n", met_on,rdma0_mode,rdma1_mode);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "pwm0:", 5) || 0 == strncmp(opt, "pwm1:", 5))
{
char *p = (char *)opt + 5;
unsigned int level = (unsigned int)simple_strtoul(p, &p, 10);
if (level)
{
disp_pwm_id_t pwm_id = DISP_PWM0;
if (opt[3] == '1')
pwm_id = DISP_PWM1;
disp_pwm_set_backlight(pwm_id, level);
sprintf(buf, "PWM 0x%x : %d\n", pwm_id, level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "aal_dbg:", 8))
{
aal_dbg_en = (int)simple_strtoul(opt + 8, NULL, 10);
sprintf(buf, "aal_dbg_en = 0x%x\n", aal_dbg_en);
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DDPMSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_NUM)
{
ddp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DDPMSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_path:", 10))
{
char *p = (char *)opt + 10;
unsigned int mutex_idx = (unsigned int) simple_strtoul(p, &p, 10);
DDPMSG("process_dbg_opt, path mutex=%d \n", mutex_idx);
dpmgr_debug_path_status(mutex_idx);
sprintf(buf, "dump_path: %d\n", mutex_idx);
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
DDPMSG("[DDP] debug=1, trigger AEE\n");
//aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_lcd_test();
}
else if(enable==4)
{
//DDPAEE("test 4");
}
else if(enable==5)
{
extern unsigned int gDDPError;
if(gDDPError==0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
}
else if(enable==6)
{
unsigned int i = 0;
int * modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
printk("dump path status:");
for(i=0;i<module_num;i++)
{
printk("%s-", ddp_get_module_name(modules[i]));
}
printk("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for( i=0; i< module_num;i++)
{
ddp_dump_analysis(modules[i]);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
for( i=0; i< module_num;i++)
{
ddp_dump_reg(modules[i]);
}
}
else if(enable==7)
{
if(dbg_log_level<3)
dbg_log_level++;
else
dbg_log_level=0;
printk("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
}
#if 0
else if(enable==8)
{
DDPDUMP("clock_mm setting:%u \n",
DISP_REG_GET(DISP_REG_CONFIG_C11));
if(DISP_REG_GET(DISP_REG_CONFIG_C11)&0xff000000!=0xff000000)
{
DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11));
}
}
#endif
else if(enable==9)
{
gOVLBackground = 0xFF0000FF;
printk("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
}
else if(enable==10)
{
gOVLBackground = 0xFF000000;
printk("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
}
else if(enable==11)
{
unsigned int i=0;
for(i=0;i<DISP_REG_NUM;i++)
{
DDPDUMP("i=%d, module=%s, reg_va=0x%lx\n", i, ddp_get_reg_module_name(i), dispsys_reg[i]);
}
}
else if(enable==12)
{
if(gUltraEnable==0)
gUltraEnable = 1;
else
gUltraEnable = 0;
printk("DDP: gUltraEnable=%d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
}
}
else if (0 == strncmp(opt, "mmp", 3))
{
init_ddp_mmp_events();
}
else
{
dbg_buf[0]='\0';
goto Error;
}
return;
Error:
DDPERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
}
static void disp_debug_api(unsigned int enable, char *buf)
{
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
/*ddp_dump_analysis(DISP_MODULE_DSI0);*/
ddp_dump_reg(DISP_MODULE_DSI0);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n",
DISP_REG_GET(DISP_REG_CONFIG_C11));
if (DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000 !=
0xff000000) {
DDPDUMP
("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
}
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
dispsys_irq[DISP_REG_NUM];
ddp_irq_num[DISP_REG_NUM];
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP
("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
sprintf(buf_temp,
"i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP : gUltraEnable = %d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
/*int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 14) {
/*int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c) = 0x%x, wdma_con2(0x38) = 0x%x, rdma_gmc0(30) = 0x%x",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0));
DDPMSG(" rdma_gmc1(38) = 0x%x, fifo_con(40) = 0x%x\n ",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG(" ovl0_gmc : 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc : 0x%x, 0x%x, 0x%x, 0x%x\n ",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug(" DDP : gDumpMemoutCmdq = %d\n ", gDumpMemoutCmdq);
sprintf(buf, " gDumpMemoutCmdq : %d\n ", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug(" DDP : gEnableSODIControl = %d\n ", gEnableSODIControl);
sprintf(buf, " gEnableSODIControl : %d\n ", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug(" DDP : gPrefetchControl = %d\n ", gPrefetchControl);
sprintf(buf, " gPrefetchControl : %d\n ", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug(" DDP : disp_low_power_enlarge_blanking = %d\n ",
disp_low_power_enlarge_blanking);
sprintf(buf, " disp_low_power_enlarge_blanking : %d\n ",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug(" DDP : disp_low_power_disable_ddp_clock = %d\n ",
disp_low_power_disable_ddp_clock);
sprintf(buf, " disp_low_power_disable_ddp_clock : %d\n ",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug(" DDP : disp_low_power_disable_fence_thread = %d\n ",
disp_low_power_disable_fence_thread);
sprintf(buf, " disp_low_power_disable_fence_thread : %d\n ",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug(" DDP : disp_low_power_remove_ovl = %d\n ", disp_low_power_remove_ovl);
sprintf(buf, " disp_low_power_remove_ovl : %d\n ", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug(" DDP : gSkipIdleDetect = %d\n ", gSkipIdleDetect);
sprintf(buf, " gSkipIdleDetect : %d\n ", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug(" DDP : gDumpClockStatus = %d\n ", gDumpClockStatus);
sprintf(buf, " gDumpClockStatus : %d\n ", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug(" DDP : gEnableUartLog = %d\n ", gEnableUartLog);
sprintf(buf, " gEnableUartLog : %d\n ", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
0);
}
pr_debug(" DDP : gEnableMutexRisingEdge = %d\n ", gEnableMutexRisingEdge);
sprintf(buf, " gEnableMutexRisingEdge : %d\n ", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug(" DDP : gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite);
sprintf(buf, " gEnableReduceRegWrite : %d\n ", gEnableReduceRegWrite);
} else if (enable == 32) {
/* DDPAEE(" DDP : (32) gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); */
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug(" DDP : gDumpConfigCMD = %d\n ", gDumpConfigCMD);
sprintf(buf, " gDumpConfigCMD : %d\n ", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug(" DDP : gESDEnableSODI = %d\n ", gESDEnableSODI);
sprintf(buf, " gESDEnableSODI : %d\n ", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug(" DDP : gEnableOVLStatusCheck = %d\n ", gEnableOVLStatusCheck);
sprintf(buf, " gEnableOVLStatusCheck : %d\n ", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug(" DDP : gResetRDMAEnable = %d\n ", gResetRDMAEnable);
sprintf(buf, " gResetRDMAEnable : %d\n ", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x3E);
} else {
gEnableIRQ = 0;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL)));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x18);
}
pr_debug(" DDP : gEnableIRQ = %d\n ", gEnableIRQ);
sprintf(buf, " gEnableIRQ : %d\n ", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug(" DDP : gDisableSODIForTriggerLoop = %d\n ", gDisableSODIForTriggerLoop);
sprintf(buf, " gDisableSODIForTriggerLoop : %d\n ", gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, " enable = %d\n ", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug(" DDP : gResetOVLInAALTrigger = %d\n ", gResetOVLInAALTrigger);
sprintf(buf, " gResetOVLInAALTrigger : %d\n ", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug(" DDP : gDisableOVLTF = %d\n ", gDisableOVLTF);
sprintf(buf, " gDisableOVLTF : %d\n ", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug(" DDP : gDumpESDCMD = %d\n ", gDumpESDCMD);
sprintf(buf, " gDumpESDCMD : %d\n ", gDumpESDCMD);
} else if (enable == 44) {
disp_dump_emi_status();
disp_dump_emi_status();
sprintf(buf, " dump emi status !\n ");
} else if (enable == 45) {
if (gEnableCMDQProfile == 0)
gEnableCMDQProfile = 1;
else
gEnableCMDQProfile = 0;
pr_debug(" DDP : gEnableCMDQProfile = %d\n ", gEnableCMDQProfile);
sprintf(buf, " gEnableCMDQProfile : %d\n ", gEnableCMDQProfile);
} else if (enable == 46) {
disp_set_pll(156);
pr_debug(" DDP : disp_set_pll = 156.\n ");
sprintf(buf, " disp_set_pll = 156.\n ");
} else if (enable == 47) {
disp_set_pll(182);
pr_debug(" DDP : disp_set_pll = 182.\n ");
sprintf(buf, " disp_set_pll = 182.\n ");
} else if (enable == 48) {
disp_set_pll(364);
pr_debug(" DDP : disp_set_pll = 364\n ");
sprintf(buf, " disp_set_pll = 364.\n ");
} else if (enable == 49) {
if (gChangeRDMAThreshold == 0)
gChangeRDMAThreshold = 1;
else
gChangeRDMAThreshold = 0;
pr_debug(" DDP : gChangeRDMAThreshold = %d\n ", gChangeRDMAThreshold);
sprintf(buf, " gChangeRDMAThreshold : %d\n ", gChangeRDMAThreshold);
} else if (enable == 50) {
if (gChangeMMClock == 0)
gChangeMMClock = 1;
else
gChangeMMClock = 0;
pr_debug(" DDP : gChangeMMClock = %d\n ", gChangeMMClock);
sprintf(buf, " gChangeMMClock : %d\n ", gChangeMMClock);
} else if (enable == 51) {
if (gEnableUnderflowAEE == 0)
gEnableUnderflowAEE = 1;
else
gEnableUnderflowAEE = 0;
pr_debug(" DDP : gEnableUnderflowAEE = %d\n ", gEnableUnderflowAEE);
sprintf(buf, " gEnableUnderflowAEE : %d\n ", gEnableUnderflowAEE);
} else if (enable == 52) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(156, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 53) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(182, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 54) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(364, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 55) {
if (gIssueRequestThreshold == 0)
gIssueRequestThreshold = 1;
else
gIssueRequestThreshold = 0;
pr_debug(" DDP : gIssueRequestThreshold = %d\n ", gIssueRequestThreshold);
sprintf(buf, " gIssueRequestThreshold : %d\n ", gIssueRequestThreshold);
} else if (enable == 56) {
if (gDisableIRQWhenIdle == 0)
gDisableIRQWhenIdle = 1;
else
gDisableIRQWhenIdle = 0;
pr_debug(" DDP : gDisableIRQWhenIdle = %d\n ", gDisableIRQWhenIdle);
sprintf(buf, " gDisableIRQWhenIdle : %d\n ", gDisableIRQWhenIdle);
} else if (enable == 57) {
if (gEnableSODIWhenIdle == 0)
gEnableSODIWhenIdle = 1;
else
gEnableSODIWhenIdle = 0;
pr_debug(" DDP : gEnableSODIWhenIdle = %d\n ", gEnableSODIWhenIdle);
sprintf(buf, " gEnableSODIWhenIdle : %d\n ", gEnableSODIWhenIdle);
} else if (enable == 58) {
#ifdef DISP_ENABLE_LAYER_FRAME
if (gAddFrame == 0)
gAddFrame = 1;
else
gAddFrame = 0;
pr_debug(" DDP : gAddFrame = %d\n ", gAddFrame);
sprintf(buf, " gAddFrame : %d\n ", gAddFrame);
#else
pr_debug(" Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
sprintf(buf, " Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
#endif
} else if (enable == 40) {
sprintf(buf, " version : %d, %s\n ", 12, __TIME__);
} else if (enable==59) {
extern void ddp_reset_test(void);
ddp_reset_test();
sprintf(buf, " dp_reset_test called. \n ");
} else if (enable == 60) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
}
}
