static int ddr_training_hardware(unsigned int mode)
{
int result = 0;
int timeout = 500000;
unsigned int pir_val = DDRP_PIR_INIT;
pir_val |= DDRP_PIR_QSTRN | DDRP_PIR_DLLLOCK;
// if(IS_BYPASS_MODE(mode))
// pir_val |= DDRP_PIR_DLLBYP | (1 << 29);
ddr_writel(pir_val, DDRP_PIR);
while ((ddr_readl(DDRP_PGSR) != (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE
| DDRP_PGSR_DIDONE
| DDRP_PGSR_DTDONE))
&& !(ddr_readl(DDRP_PGSR)
& (DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR))
&& --timeout);
if (timeout == 0) {
dwc_debug("DDR training timeout\n");
result = -1;
} else if (ddr_readl(DDRP_PGSR)
& (DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR)) {
dwc_debug("DDR hardware training error\n");
result = ddr_readl(DDRP_PGSR);
}
return result;
}
static int ddr_training_software(unsigned int mode)
{
unsigned int result = 0;
unsigned int ddr_bl, ddr_cl;
unsigned int mr0_tmp = 1;
unsigned int cs0;
unsigned int cs1;
unsigned int tmp = 0;
dwc_debug("Now try soft training\n");
#ifdef CONFIG_DDR_HOST_CC
cs0 = CONFIG_DDR_CS0;
cs1 = CONFIG_DDR_CS1;
#else /* CONFIG_DDR_HOST_CC */
cs0 = ddr_params_p->cs0;
cs1 = ddr_params_p->cs1;
#endif /* CONFIG_DDR_HOST_CC */
if (dqs_gate_train(cs0 + cs1, 4)) {
dwc_debug("DDR soft train fail too!!!\n");
dump_ddrp_register();
result = 1;
}
if((result) && (!cs1)){
printf("try again to soft train may be the problem for cs\n");
tmp = ddr_readl(DDRC_CFG);
tmp |= 3 << 6;
ddr_writel(tmp, DDRC_CFG);
if (dqs_gate_train(cs0, 4)) {
dwc_debug("try again DDR soft train fail too please check the hardware!!!\n");
dump_ddrp_register();
result = -1;
}
}
#ifdef CONFIG_DDR_HOST_CC
ddr_bl = DDR_BL;
ddr_cl = DDR_CL;
#else /* CONFIG_DDR_HOST_CC */
ddr_cl = ddr_params_p->cl;
ddr_bl = ddr_params_p->bl;
#endif /* CONFIG_DDR_HOST_CC */
if(DDR_TYPE_MODE(mode) == LPDDR){
while (ddr_bl >> mr0_tmp)
mr0_tmp++;
ddr_writel((ddr_cl << 4) | (mr0_tmp - 1), DDRP_MR0);
send_MR0(ddr_readl(DDRP_MR0));
}
return result;
}
static void ddr_chip_init(unsigned int mode)
{
int timeout = 10000;
unsigned int pir_val = DDRP_PIR_INIT;
unsigned int val;
dwc_debug("DDR chip init\n");
// DDRP_PIR_DRAMRST for ddr3 only
#ifndef CONFIG_FPGA
pir_val |= DDRP_PIR_DRAMINT | DDRP_PIR_DLLSRST;
#else
pir_val |= DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST | DDRP_PIR_DLLBYP;
#endif
// if(IS_BYPASS_MODE(mode)) {
// pir_val |= DDRP_PIR_DLLBYP | (1 << 29);
// pir_val &= ~DDRP_PIR_DLLSRST;
// // DLL Disable: only bypassmode
// ddr_writel(0x1 << 31, DDRP_ACDLLCR);
// val = ddr_readl(DDRP_DSGCR);
// /* LPDLLPD: only for ddr bypass mode
// * Low Power DLL Power Down: Specifies if set that the PHY should respond to the *
// * DFI low power opportunity request and power down the DLL of the PHY if the *
// * wakeup time request satisfies the DLL lock time */
// val &= ~(1 << 4);
// ddr_writel(val,DDRP_DSGCR);
//
// val = ddr_readl(DDRP_DLLGCR);
// val |= 1 << 23;
// ddr_writel(val,DDRP_DLLGCR);
//
// }
ddr_writel(pir_val, DDRP_PIR);
while (!(ddr_readl(DDRP_PGSR) == (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE
| DDRP_PGSR_DIDONE))
&& (ddr_readl(DDRP_PGSR) != 0x1f)
&& --timeout);
if (timeout == 0) {
printf("DDR init timeout: PGSR=%X\n", ddr_readl(DDRP_PGSR));
hang();
}
}
static void remap_swap(int a, int b)
{
uint32_t remmap[2], tmp[2];
remmap[0] = ddr_readl(DDRC_REMAP(a / 4 + 1));
remmap[1] = ddr_readl(DDRC_REMAP(b / 4 + 1));
#define BIT(bit) ((bit % 4) * 8)
#define MASK(bit) (0x1f << BIT(bit))
tmp[0] = (remmap[0] & MASK(a)) >> BIT(a);
tmp[1] = (remmap[1] & MASK(b)) >> BIT(b);
remmap[0] &= ~MASK(a);
remmap[1] &= ~MASK(b);
ddr_writel(remmap[0] | (tmp[1] << BIT(a)), DDRC_REMAP(a / 4 + 1));
ddr_writel(remmap[1] | (tmp[0] << BIT(b)), DDRC_REMAP(b / 4 + 1));
#undef BIT
#undef MASK
}
static int lpddr_retrain_bypass(void)
{
unsigned int result = 0;
int timeout = 10000;
unsigned int ddr_bl, ddr_cl;
unsigned int mr0_tmp = 1;
#ifdef CONFIG_DDR_HOST_CC
ddr_bl = DDR_BL;
ddr_cl = DDR_CL;
#else /* CONFIG_DDR_HOST_CC */
ddr_cl = ddr_params_p->cl;
ddr_bl = ddr_params_p->bl;
#endif /* CONFIG_DDR_HOST_CC */
while (ddr_bl >> mr0_tmp)
mr0_tmp++;
ddr_writel((ddr_cl << 4) | (mr0_tmp - 1), DDRP_MR0);
#ifndef CONFIG_DDR_PHY_ODT
ddr_writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT, DDRP_PIR);
#else /* CONFIG_DDR_PHY_ODT */
ddr_writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DLLLOCK | DDRP_PIR_DLLBYP | (1 << 29),
DDRP_PIR);
ddr_writel(0x1, DDRP_ACDLLCR);
#endif /* CONFIG_DDR_PHY_ODT */
while ((ddr_readl(DDRP_PGSR) != (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE
| DDRP_PGSR_DIDONE
| DDRP_PGSR_DTDONE))
&& --timeout);
if (timeout == 0) {
printf("DDR PHY init timeout: PGSR=%X\n", ddr_readl(DDRP_PGSR));
result = -1;
}
return result;
}
static int __init init_ddr_proc(void)
{
struct proc_dir_entry *p;
#ifdef CONFIG_DDR_DEBUG
register int bypassmode = 0;
register int AutoSR_en = 0;
bypassmode = ddr_readl(DDRP_PIR) & DDRP_PIR_DLLBYP;
if(bypassmode) {
printk("the ddr is in bypass mode\n");
}else{
printk("the ddr it not in bypass mode\n");
}
AutoSR_en = ddr_readl(DDRC_AUTOSR_EN) & DDRC_AUTOSR_ENABLE;
if(AutoSR_en) {
printk("the ddr self_refresh is enable\n");
}else{
printk("the ddr self_refrese is not enable\n");
}
printk("the ddr remap register is\n");
printk("DDRC_REMAP1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(1)),DDRC_BASE + DDRC_REMAP(1));
printk("DDRC_REMAP2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(2)),DDRC_BASE + DDRC_REMAP(2));
printk("DDRC_REMAP3\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(3)),DDRC_BASE + DDRC_REMAP(3));
printk("DDRC_REMAP4\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(4)),DDRC_BASE + DDRC_REMAP(4));
printk("DDRC_REMAP5\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(5)),DDRC_BASE + DDRC_REMAP(5));
#endif
printk("%d,%s\n",__LINE__,__func__);
p = jz_proc_mkdir("ddr");
if (!p) {
pr_warning("create_proc_entry for common ddr failed.\n");
return -ENODEV;
}
proc_create_data("ddr_Register", 0444, p, &ddr_register_proc_fops, 0);
proc_create_data("ddr_monitor1", 0444, p, &ddr_mon1_proc_fops, 0);
proc_create_data("ddr_monitor2", 0444, p, &ddr_mon2_proc_fops, 0);
proc_create_data("ddr_monitor3", 0444, p, &ddr_mon3_proc_fops, 0);
return 0;
}
static void ddr_impedance_matching(void)
{
#if defined(CONFIG_DDR_PHY_IMPED_PULLUP) && defined(CONFIG_DDR_PHY_IMPED_PULLDOWN)
/**
* DDR3 240ohm RZQ output impedance:
* 55.1ohm 0xc
* 49.2ohm 0xd
* 44.5ohm 0xe
* 40.6ohm 0xf
* 37.4ohm 0xa
* 34.7ohm 0xb
* 32.4ohm 0x8
* 30.4ohm 0x9
* 28.6ohm 0x18
*/
unsigned int i;
i = ddr_readl(DDRP_ZQXCR0(0)) & ~0x3ff;
i |= DDRP_ZQXCR_ZDEN
| ((CONFIG_DDR_PHY_IMPED_PULLUP & 0x1f) << DDRP_ZQXCR_PULLUP_IMPED_BIT)
| ((CONFIG_DDR_PHY_IMPED_PULLDOWN & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPED_BIT);
ddr_writel(i, DDRP_ZQXCR0(0));
#endif
}
static void ddr_training(unsigned int mode)
{
unsigned int training_state = -1;
dwc_debug("DDR training\n");
#ifndef CONFIG_DDR_FORCE_SOFT_TRAINING
training_state = ddr_training_hardware(mode);
#endif
if(training_state)
{
int i = 0;
for (i = 0; i < 4; i++) {
dwc_debug("DX%dGSR0: %x\n", i, ddr_readl(DDRP_DXGSR0(i)));
}
dump_ddrp_register();
#ifdef CONFIG_SPL_DDR_SOFT_TRAINING
training_state = ddr_training_software(mode);
#endif // CONFIG_SPL_DDR_SOFT_TRAINING
}
if(DDR_TYPE_MODE(mode) == LPDDR)
training_state = lpddr_retrain_bypass();
if(training_state)
hang();
}
static int dump_out_ddr(struct seq_file *m, void *v)
{
int len = 0;
int i = 0;
len += seq_printf(m ,"--------------------dump the DDRC1---------------\n");
len += seq_printf(m ,"DDRC_STATUS\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_STATUS),DDRC_BASE + DDRC_STATUS);
len += seq_printf(m ,"DDRC_CFG\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_CFG),DDRC_BASE + DDRC_CFG);
len += seq_printf(m ,"DDRC_CTRL\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_CTRL),DDRC_BASE + DDRC_CTRL);
len += seq_printf(m ,"DDRC_LMR\t:0x%08x\taddress\t:0x%08x\n",ddr_readl(DDRC_LMR),DDRC_BASE + DDRC_LMR);
len += seq_printf(m ,"DDRC_TIMING1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(1)),DDRC_BASE + DDRC_TIMING(1));
len += seq_printf(m ,"DDRC_TIMING2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(2)),DDRC_BASE + DDRC_TIMING(2));
len += seq_printf(m ,"DDRC_TIMING3\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(3)),DDRC_BASE + DDRC_TIMING(3));
len += seq_printf(m ,"DDRC_TIMING4\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(4)),DDRC_BASE + DDRC_TIMING(4));
len += seq_printf(m ,"DDRC_TIMING5\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(5)),DDRC_BASE + DDRC_TIMING(5));
len += seq_printf(m ,"DDRC_TIMING6\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_TIMING(6)),DDRC_BASE + DDRC_TIMING(6));
len += seq_printf(m ,"DDRC_REFCNT\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REFCNT),DDRC_BASE + DDRC_REFCNT);
len += seq_printf(m ,"DDRC_MMAP0\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_MMAP0),DDRC_BASE + DDRC_MMAP0);
len += seq_printf(m ,"DDRC_MMAP1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_MMAP1),DDRC_BASE + DDRC_MMAP1);
len += seq_printf(m ,"DDRC_REMAP1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(1)),DDRC_BASE + DDRC_REMAP(1));
len += seq_printf(m ,"DDRC_REMAP2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(2)),DDRC_BASE + DDRC_REMAP(2));
len += seq_printf(m ,"DDRC_REMAP3\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(3)),DDRC_BASE + DDRC_REMAP(3));
len += seq_printf(m ,"DDRC_REMAP4\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(4)),DDRC_BASE + DDRC_REMAP(4));
len += seq_printf(m ,"DDRC_REMAP5\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_REMAP(5)),DDRC_BASE + DDRC_REMAP(5));
len += seq_printf(m ,"DDRC_AUTOSR_EN\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRC_AUTOSR_EN),DDRC_BASE + DDRC_AUTOSR_EN);
len += seq_printf(m ,"--------------------dump the DDRP---------------\n");
len += seq_printf(m ,"DDRP_PIR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PIR),DDRC_BASE + DDRP_PIR);
len += seq_printf(m ,"DDRP_PGCR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PGCR),DDRC_BASE + DDRP_PGCR);
len += seq_printf(m ,"DDRP_PGSR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PGSR),DDRC_BASE + DDRP_PGSR);
len += seq_printf(m ,"DDRP_PTR0\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PTR0),DDRC_BASE + DDRP_PTR0);
len += seq_printf(m ,"DDRP_PTR1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PTR1),DDRC_BASE + DDRP_PTR1);
len += seq_printf(m ,"DDRP_PTR2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_PTR2),DDRC_BASE + DDRP_PTR2);
len += seq_printf(m ,"DDRP_DSGCR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_DSGCR),DDRC_BASE + DDRP_DSGCR);
len += seq_printf(m ,"DDRP_DCR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_DCR),DDRC_BASE + DDRP_DCR);
len += seq_printf(m ,"DDRP_DTPR0\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_DTPR0),DDRC_BASE + DDRP_DTPR0);
len += seq_printf(m ,"DDRP_DTPR1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_DTPR1),DDRC_BASE + DDRP_DTPR1);
len += seq_printf(m ,"DDRP_DTPR2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_DTPR2),DDRC_BASE + DDRP_DTPR2);
len += seq_printf(m ,"DDRP_MR0\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_MR0),DDRC_BASE + DDRP_MR0);
len += seq_printf(m ,"DDRP_MR1\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_MR1),DDRC_BASE + DDRP_MR1);
len += seq_printf(m ,"DDRP_MR2\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_MR2),DDRC_BASE + DDRP_MR2);
len += seq_printf(m ,"DDRP_MR3\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_MR3),DDRC_BASE + DDRP_MR3);
len += seq_printf(m ,"DDRP_ODTCR\t:0x%08x\taddress\t:0x%08x\n", ddr_readl(DDRP_ODTCR),DDRC_BASE + DDRP_ODTCR);
for(i=0;i<4;i++) {
len += seq_printf(m ,"DX%dGSR0 \t:0x%08x\taddress\t:0x%08x\n", i, ddr_readl(DDRP_DXGSR0(i)),DDRC_BASE + DDRP_DXGSR0(i));
len += seq_printf(m ,"@pas:DXDQSTR(%d)\t:0x%08x\taddress\t:0x%08x\n", i,ddr_readl(DDRP_DXDQSTR(i)),DDRC_BASE + DDRP_DXDQSTR(i));
}
return len;
}
static void dump_ddrc_register(void)
{
#ifdef CONFIG_DWC_DEBUG
printf("DDRC_STATUS 0x%x\n", ddr_readl(DDRC_STATUS));
printf("DDRC_CFG 0x%x\n", ddr_readl(DDRC_CFG));
printf("DDRC_CTRL 0x%x\n", ddr_readl(DDRC_CTRL));
printf("DDRC_LMR 0x%x\n", ddr_readl(DDRC_LMR));
printf("DDRC_TIMING1 0x%x\n", ddr_readl(DDRC_TIMING(1)));
printf("DDRC_TIMING2 0x%x\n", ddr_readl(DDRC_TIMING(2)));
printf("DDRC_TIMING3 0x%x\n", ddr_readl(DDRC_TIMING(3)));
printf("DDRC_TIMING4 0x%x\n", ddr_readl(DDRC_TIMING(4)));
printf("DDRC_TIMING5 0x%x\n", ddr_readl(DDRC_TIMING(5)));
printf("DDRC_TIMING6 0x%x\n", ddr_readl(DDRC_TIMING(6)));
printf("DDRC_REFCNT 0x%x\n", ddr_readl(DDRC_REFCNT));
printf("DDRC_MMAP0 0x%x\n", ddr_readl(DDRC_MMAP0));
printf("DDRC_MMAP1 0x%x\n", ddr_readl(DDRC_MMAP1));
printf("DDRC_REMAP1 0x%x\n", ddr_readl(DDRC_REMAP(1)));
printf("DDRC_REMAP2 0x%x\n", ddr_readl(DDRC_REMAP(2)));
printf("DDRC_REMAP3 0x%x\n", ddr_readl(DDRC_REMAP(3)));
printf("DDRC_REMAP4 0x%x\n", ddr_readl(DDRC_REMAP(4)));
printf("DDRC_REMAP5 0x%x\n", ddr_readl(DDRC_REMAP(5)));
#endif
}
/* DDR sdram init */
void sdram_init(void)
{
int type = VARIABLE;
unsigned int mode;
unsigned int bypass = 0;
unsigned int rate;
#ifdef CONFIG_DDR_TYPE_DDR3
type = DDR3;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR
type = LPDDR;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR2
type = LPDDR2;
#endif
#ifdef CONFIG_DDR_TYPE_DDR2
type = DDR2;
#endif
#ifndef CONFIG_DDR_HOST_CC
struct ddrc_reg ddrc;
struct ddrp_reg ddrp;
#ifndef CONFIG_DDR_TYPE_VARIABLE
struct ddr_params ddr_params;
ddr_params_p = &ddr_params;
#else
ddr_params_p = &gd->arch.gi->ddr_params;
ddr_params_p->freq = gd->arch.gi->cpufreq / gd->arch.gi->ddr_div;
#endif
fill_in_params(ddr_params_p, type);
ddr_params_creator(&ddrc, &ddrp, ddr_params_p);
ddr_params_assign(&ddrc, &ddrp, ddr_params_p);
#endif /* CONFIG_DDR_HOST_CC */
dwc_debug("sdram init start\n");
#ifndef CONFIG_FPGA
clk_set_rate(DDR, gd->arch.gi->ddrfreq);
reset_dll();
rate = clk_get_rate(DDR);
#else
rate = gd->arch.gi->ddrfreq;
#endif
#ifdef CONFIG_M200
if(rate <= 150000000)
bypass = 1;
#endif
reset_controller();
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
ddr_writel(0x0 ,DDRC_AUTOSR_EN);
#endif
/*force CKE1 HIGH*/
ddr_writel(DDRC_CFG_VALUE, DDRC_CFG);
ddr_writel((1 << 1), DDRC_CTRL);
mode = (type << 1) | (bypass & 1);
/* DDR PHY init*/
ddr_phy_init(mode);
dump_ddrp_register();
ddr_writel(0, DDRC_CTRL);
/* DDR Controller init*/
ddr_controller_init();
dump_ddrc_register();
/* DDRC address remap configure*/
// mem_remap();
ddr_writel(ddr_readl(DDRC_STATUS) & ~DDRC_DSTATUS_MISS, DDRC_STATUS);
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
if(!bypass)
ddr_writel(0 , DDRC_DLP);
ddr_writel(0x1 ,DDRC_AUTOSR_EN);
#endif
dwc_debug("sdram init finished\n");
#undef DDRTYPE
}
static void ddr_phy_param_init(unsigned int mode)
{
int i;
unsigned int timeout = 10000;
ddr_writel(DDRP_DCR_VALUE, DDRP_DCR);
ddr_writel(DDRP_MR0_VALUE, DDRP_MR0);
ddr_writel(DDRP_MR3_VALUE, DDRP_MR3);
#ifdef CONFIG_SYS_DDR_CHIP_ODT
ddr_writel(0, DDRP_ODTCR);
#endif
ddr_writel(DDRP_PTR0_VALUE, DDRP_PTR0);
ddr_writel(DDRP_PTR1_VALUE, DDRP_PTR1);
ddr_writel(DDRP_PTR2_VALUE, DDRP_PTR2);
ddr_writel(DDRP_DTPR0_VALUE, DDRP_DTPR0);
ddr_writel(DDRP_DTPR1_VALUE, DDRP_DTPR1);
ddr_writel(DDRP_DTPR2_VALUE, DDRP_DTPR2);
// for (i = 0; i < 4; i++) {
// unsigned int tmp = ddr_readl(DDRP_DXGCR(i));
//
// tmp &= ~(3 << 9);
//#ifdef CONFIG_DDR_PHY_ODT
//#ifdef CONFIG_DDR_PHY_DQ_ODT
// tmp |= 1 << 10;
//#endif /* CONFIG_DDR_PHY_DQ_ODT */
//#ifdef CONFIG_DDR_PHY_DQS_ODT
// tmp |= 1 << 9;
//#endif /* CONFIG_DDR_PHY_DQS_ODT */
//#endif /* CONFIG_DDR_PHY_ODT */
//#ifndef CONFIG_DDR_HOST_CC
// if ((i > 1) && (ddr_params_p->dw32 == 0))
// tmp &= ~DDRP_DXGCR_DXEN;
//#elif (CONFIG_DDR_DW32 == 0)
// if (i > 1)
// tmp &= ~DDRP_DXGCR_DXEN;
//#endif /* CONFIG_DDR_HOST_CC */
// ddr_writel(tmp, DDRP_DXGCR(i));
// }
ddr_writel(DDRP_PGCR_VALUE, DDRP_PGCR);
/***************************************************************
* DXCCR:
* DQSRES: 4...7bit is DQSRES[].
* DQSNRES: 8...11bit is DQSRES[] too.
*
* Selects the on-die pull-down/pull-up resistor for DQS pins.
* DQSRES[3]: selects pull-down (when set to 0) or pull-up (when set to 1).
* DQSRES[2:0] selects the resistor value as follows:
* 000 = Open: On-die resistor disconnected
* 001 = 688 ohms
* 010 = 611 ohms
* 011 = 550 ohms
* 100 = 500 ohms
* 101 = 458 ohms
* 110 = 393 ohms
* 111 = 344 ohms
*****************************************************************
* Note: DQS resistor must be connected for LPDDR/LPDDR2 *
*****************************************************************
* the config will affect power and stablity
*/
ddr_writel(0x30c00813, DDRP_ACIOCR);
ddr_writel(0x4802, DDRP_DXCCR);
while (!(ddr_readl(DDRP_PGSR) == (DDRP_PGSR_IDONE
| DDRP_PGSR_DLDONE
| DDRP_PGSR_ZCDONE))
&& (ddr_readl(DDRP_PGSR) != 0x1f)
&& --timeout);
if (timeout == 0) {
printf("DDR PHY init timeout: PGSR=%X\n", ddr_readl(DDRP_PGSR));
hang();
}
}
static void dump_ddrp_register(void)
{
#ifdef CONFIG_DWC_DEBUG
printf("DDRP_PIR 0x%x\n", ddr_readl(DDRP_PIR));
printf("DDRP_PGCR 0x%x\n", ddr_readl(DDRP_PGCR));
printf("DDRP_PGSR 0x%x\n", ddr_readl(DDRP_PGSR));
printf("DDRP_PTR0 0x%x\n", ddr_readl(DDRP_PTR0));
printf("DDRP_PTR1 0x%x\n", ddr_readl(DDRP_PTR1));
printf("DDRP_PTR2 0x%x\n", ddr_readl(DDRP_PTR2));
printf("DDRP_DCR 0x%x\n", ddr_readl(DDRP_DCR));
printf("DDRP_DTPR0 0x%x\n", ddr_readl(DDRP_DTPR0));
printf("DDRP_DTPR1 0x%x\n", ddr_readl(DDRP_DTPR1));
printf("DDRP_DTPR2 0x%x\n", ddr_readl(DDRP_DTPR2));
printf("DDRP_MR0 0x%x\n", ddr_readl(DDRP_MR0));
printf("DDRP_MR1 0x%x\n", ddr_readl(DDRP_MR1));
printf("DDRP_MR2 0x%x\n", ddr_readl(DDRP_MR2));
printf("DDRP_MR3 0x%x\n", ddr_readl(DDRP_MR3));
printf("DDRP_ODTCR 0x%x\n", ddr_readl(DDRP_ODTCR));
int i=0;
for(i=0;i<4;i++) {
printf("DX%dGSR0: %x\n", i, ddr_readl(DDRP_DXGSR0(i)));
printf("@pas:DXDQSTR(%d)= 0x%x\n", i,ddr_readl(DDRP_DXDQSTR(i)));
}
#endif
}
