static void ddramc_init(void)
{
unsigned long csa;
struct ddramc_register ddramc_reg;
ddramc_reg_config(&ddramc_reg);
/* ENABLE DDR2 clock */
writel(AT91C_PMC_DDR, AT91C_BASE_PMC + PMC_SCER);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
csa |= AT91C_EBI_CS1A_SDRAMC;
csa &= ~AT91C_VDDIOM_SEL_33V;
writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_DDRAM_BASE_ADDR, &ddramc_reg);
/*
* EBI IO in 1.8V mode
*/
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) & ~(1 << 16),
AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* EBI DDRAM controller
*/
ddram_initialize(AT91C_BASE_DDRSDRC1, AT91C_BASE_CS1, &ddramc_reg);
}
static void ddramc_init(void)
{
struct ddramc_register ddramc_reg;
unsigned int reg;
ddramc_reg_config(&ddramc_reg);
/* enable ddr2 clock */
writel(1 << (AT91C_ID_MPDDRC - 32), (PMC_PCER1 + AT91C_BASE_PMC));
writel(AT91C_PMC_DDR, (PMC_SCER + AT91C_BASE_PMC));
/* Init the special register for sama5d3x */
/* MPDDRC DLL Slave Offset Register: DDR2 configuration */
reg = AT91C_MPDDRC_S0OFF_1
| AT91C_MPDDRC_S2OFF_1
| AT91C_MPDDRC_S3OFF_1;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_DLL_SOR));
/* MPDDRC DLL Master Offset Register */
/* write master + clk90 offset */
reg = AT91C_MPDDRC_MOFF_7
| AT91C_MPDDRC_CLK90OFF_31
| AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_DLL_MOR));
/* MPDDRC I/O Calibration Register */
/* DDR2 RZQ = 50 Ohm */
/* TZQIO = 4 */
reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
| AT91C_MPDDRC_TZQIO_4;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR));
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg);
}
static void ddramc_init(void)
{
struct ddramc_register ddramc_reg;
unsigned int reg;
ddramc_reg_config(&ddramc_reg);
pmc_sam9x5_enable_periph_clk(AT91C_ID_MPDDRC);
pmc_enable_system_clock(AT91C_PMC_DDR);
/* MPDDRC I/O Calibration Register */
reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR);
reg &= ~AT91C_MPDDRC_RDIV;
reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50;
reg &= ~AT91C_MPDDRC_TZQIO;
reg |= AT91C_MPDDRC_TZQIO_(100);
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR));
writel(AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES,
(AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH));
ddr3_sdram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg);
ddramc_dump_regs(AT91C_BASE_MPDDRC);
}
static void ddramc_init(void)
{
unsigned long csa;
struct ddramc_register ddramc_reg;
ddramc_reg_config(&ddramc_reg);
/* ENABLE DDR2 clock */
pmc_enable_system_clock(AT91C_PMC_DDR);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
csa |= AT91C_EBI_CS1A_SDRAMC;
/*
csa &= ~AT91C_EBI_DBPUC;
csa |= AT91C_EBI_DBPDC;
csa |= AT91C_EBI_DRV_HD;
*/
writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg);
}
static void ddramc_init(void)
{
struct ddramc_register ddramc_reg;
unsigned int reg;
ddramc_reg_config(&ddramc_reg);
/* enable ddr2 clock */
pmc_enable_periph_clock(AT91C_ID_MPDDRC);
pmc_enable_system_clock(AT91C_PMC_DDR);
/* configure Shift Sampling Point of Data */
#if defined(CONFIG_BUS_SPEED_148MHZ)
reg = AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT;
#elif defined(CONFIG_BUS_SPEED_200MHZ)
reg = AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES;
#else
reg = AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES;
#endif
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH));
/* MPDDRC I/O Calibration Register */
reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR);
reg &= ~AT91C_MPDDRC_RDIV;
reg &= ~AT91C_MPDDRC_TZQIO;
reg &= ~AT91C_MPDDRC_CALCODEP;
reg &= ~AT91C_MPDDRC_CALCODEN;
reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50;
#if defined(CONFIG_BUS_SPEED_148MHZ)
reg |= AT91C_MPDDRC_TZQIO_4; /* @ 133 & 148 MHz */
#else
reg |= AT91C_MPDDRC_TZQIO_5; /* @ 170 & 176 MHz */
#endif
reg |= AT91C_MPDDRC_EN_CALIB;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR));
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg);
ddramc_dump_regs(AT91C_BASE_MPDDRC);
}