int32_t dac_data_setup(dac_core *core) { dac_channel *chan; uint32_t i; for (i = 0; i < core->no_of_channels; i++) { chan = &core->channels[i]; if (chan->sel == DAC_SRC_DDS) { dds_set_frequency(core, ((i*2)+0), chan->dds_frequency_tone0); dds_set_phase(core, ((i*2)+0), chan->dds_phase_tone0); dds_set_scale(core, ((i*2)+0), chan->dds_scale_tone0); if (chan->dds_dual_tone == 0) { dds_set_frequency(core, ((i*2)+1), chan->dds_frequency_tone0); dds_set_phase(core, ((i*2)+1), chan->dds_phase_tone0); dds_set_scale(core, ((i*2)+1), chan->dds_scale_tone0); } else { dds_set_frequency(core, ((i*2)+1), chan->dds_frequency_tone1); dds_set_phase(core, ((i*2)+1), chan->dds_phase_tone1); dds_set_scale(core, ((i*2)+1), chan->dds_scale_tone1); } } dac_write(core, DAC_REG_DATA_PATTERN(i), chan->pat_data); dac_data_src_sel(core, i, chan->sel); } return(0); }
/**************************************************************************//*** * @brief Sets the DDS TX2 Tone 2 scale. * * @return None. *******************************************************************************/ void set_dds_tx2_tone2_scale(double* param, char param_no) // dds_tx2_tone2_scale= { uint32_t scale = (uint32_t)param[0]; if(param_no >= 1) { dds_set_scale(DDS_CHAN_TX2_I_F2, scale); dds_set_scale(DDS_CHAN_TX2_Q_F2, scale); console_print("dds_tx2_tone2_scale=%d\n", scale); } else show_invalid_param_message(1); }
/**************************************************************************//*** * @brief Sets the DDS TX2 Tone 2 scale. * * @return None. *******************************************************************************/ void set_dds_tx2_tone2_scale(double* param, char param_no) // dds_tx2_tone2_scale= { double scale = param[0]; if(param_no >= 1) { dds_set_scale(DDS_CHAN_TX2_I_F2, scale); dds_set_scale(DDS_CHAN_TX2_Q_F2, scale); scale = dds_st.cached_scale[DDS_CHAN_TX2_I_F2]; console_print("dds_tx2_tone2_scale=%f\n", scale); } else show_invalid_param_message(1); }
/**************************************************************************//*** * @brief Sets the DDS TX2 Tone 1 scale. * * @return None. *******************************************************************************/ void set_dds_tx2_tone1_scale(double* param, char param_no) // dds_tx2_tone1_scale= { int32_t scale = (int32_t)param[0]; if(param_no >= 1) { dds_set_scale(ad9361_phy, DDS_CHAN_TX2_I_F1, scale); dds_set_scale(ad9361_phy, DDS_CHAN_TX2_Q_F1, scale); scale = dds_st.cached_scale[DDS_CHAN_TX2_I_F1]; console_print("dds_tx2_tone1_scale=%d\n", scale); } else show_invalid_param_message(1); }
/**************************************************************************//*** * @brief Sets the DDS TX1 Tone 1 scale. * * @return None. *******************************************************************************/ void set_dds_tx1_tone1_scale(double* param, char param_no) // dds_tx1_tone1_scale= { int32_t scale = (int32_t)param[0]; if (ad9361_phy==0) { console_print ("Error: no AD9361 device selected\n"); return; } if(param_no >= 1) { dds_set_scale(DDS_CHAN_TX1_I_F1, scale, ad9361_phy); dds_set_scale(DDS_CHAN_TX1_Q_F1, scale, ad9361_phy); scale = ad9361_phy->dds_st.cached_scale[DDS_CHAN_TX1_I_F1]; console_print("dds_tx1_tone1_scale=%d\n", scale); } else show_invalid_param_message(1); }
/***************************************************************************//** * @brief dds_update *******************************************************************************/ void dds_update(void) { uint32_t chan; for(chan = DDS_CHAN_TX1_I_F1; chan <= DDS_CHAN_TX2_Q_F2; chan++) { dds_set_frequency(chan, dds_st.cached_freq[chan]); dds_set_phase(chan, dds_st.cached_phase[chan]); dds_set_scale(chan, dds_st.cached_scale[chan]); } }
/***************************************************************************//** * @brief dds_update *******************************************************************************/ void dds_update(struct ad9361_rf_phy *phy) { uint32_t chan; for(chan = DDS_CHAN_TX1_I_F1; chan <= DDS_CHAN_TX2_Q_F2; chan++) { dds_set_frequency(phy, chan, dds_st[phy->id_no].cached_freq[chan]); dds_set_phase(phy, chan, dds_st[phy->id_no].cached_phase[chan]); dds_set_scale(phy, chan, dds_st[phy->id_no].cached_scale[chan]); } }
/***************************************************************************//** * @brief main *******************************************************************************/ int main(void) { adf4350_setup(SPI_DEVICE_ID, 0, default_adf4350_init_param); dac_setup(XPAR_AXI_AD9739A_BASEADDR); ad9739a_setup(SPI_DEVICE_ID, 1, default_ad9739a_init_param); dac_write(ADI_REG_CNTRL_2, ADI_DATA_FORMAT); dds_set_frequency(0, 300000000); dds_set_phase(0, 0); dds_set_scale(0, 250000); dds_set_frequency(1, 300000000); dds_set_phase(1, 0); dds_set_scale(1, 250000); return 0; }
/***************************************************************************//** * @brief dds_default_setup *******************************************************************************/ static int dds_default_setup(uint32_t chan, uint32_t phase, uint32_t freq, double scale) { dds_set_phase(chan, phase); dds_set_frequency(chan, freq); dds_set_scale(chan, scale); dds_st.cached_freq[chan] = freq; dds_st.cached_phase[chan] = phase; dds_st.cached_scale[chan] = scale; return 0; }
/***************************************************************************//** * @brief dds_default_setup *******************************************************************************/ static int dds_default_setup(struct ad9361_rf_phy *phy, uint32_t chan, uint32_t phase, uint32_t freq, int32_t scale) { dds_set_phase(phy, chan, phase); dds_set_frequency(phy, chan, freq); dds_set_scale(phy, chan, scale); dds_st[phy->id_no].cached_freq[chan] = freq; dds_st[phy->id_no].cached_phase[chan] = phase; dds_st[phy->id_no].cached_scale[chan] = scale; return 0; }
/***************************************************************************//** * @brief main *******************************************************************************/ int main(void) { jesd204b_gt_state jesd204b_gt_st; jesd204b_state jesd204b_st; daq2_gpio_ctl(GPIO_BASEADDR); ad9523_setup(SPI_DEVICE_ID, 0, ad9523_pdata_lpc); ad9144_setup(SPI_DEVICE_ID, 1, default_ad9144_init_param); jesd204b_st.lanesync_enable = 1; jesd204b_st.scramble_enable = 1; jesd204b_st.sysref_always_enable = 0; jesd204b_st.frames_per_multiframe = 32; jesd204b_st.bytes_per_frame = 1; jesd204b_st.subclass = 1; jesd204b_setup(AD9144_JESD_BASEADDR, jesd204b_st); ad9680_setup(SPI_DEVICE_ID, 2); jesd204b_st.lanesync_enable = 1; jesd204b_st.scramble_enable = 1; jesd204b_st.sysref_always_enable = 0; jesd204b_st.frames_per_multiframe = 32; jesd204b_st.bytes_per_frame = 1; jesd204b_st.subclass = 1; jesd204b_setup(AD9680_JESD_BASEADDR, jesd204b_st); jesd204b_gt_st.use_cpll = 0; jesd204b_gt_st.rx_sys_clk_sel = 3; jesd204b_gt_st.rx_out_clk_sel = 4; jesd204b_gt_st.tx_sys_clk_sel = 3; jesd204b_gt_st.tx_out_clk_sel = 4; jesd204b_gt_setup(DAQ2_GT_BASEADDR, jesd204b_gt_st); jesd204b_gt_clk_enable(JESD204B_GT_TX); jesd204b_gt_clk_enable(JESD204B_GT_RX); jesd204b_gt_clk_synchronize(JESD204B_GT_TX); jesd204b_gt_clk_synchronize(JESD204B_GT_RX); dac_setup(AD9144_CORE_BASEADDR); dds_set_frequency(0, 5000000); dds_set_phase(0, 0); dds_set_scale(0, 500000); dds_set_frequency(1, 5000000); dds_set_phase(1, 0); dds_set_scale(1, 500000); dds_set_frequency(2, 5000000); dds_set_phase(2, 90000); dds_set_scale(2, 500000); dds_set_frequency(3, 5000000); dds_set_phase(3, 90000); dds_set_scale(3, 500000); adc_setup(AD9680_CORE_BASEADDR, AD9680_DMA_BASEADDR, 2); xil_printf("Done.\n\r"); return 0; }