int clk_set_rate_test_case0(void)
{
struct clk *sio_bclk = clk_get(NULL,"sio_bclk");
int ret = 0;
ret = clk_set_rate(sio_bclk, TCXO/4);
if (ret){
clk_printf("sio_bclk set rate TCXO/4,failure\n");
return CLK_TEST_ERROR;
}
clk_set_rate(sio_bclk, TCXO);
debug_clock();
debug_clk_enable(30);
debug_clk_disable(30);
debug_clk_set_rate(30,100);
debug_clk_get_rate(30);
debug_clk_set_parent(30,31);
debug_clk_status(30);
debug_clk_enable(14);
debug_clk_disable(14);
debug_clk_set_rate(14,100);
debug_clk_get_rate(14);
debug_clk_set_parent(14,15);
debug_clk_status(14);
return CLK_TEST_OK;
}
void loop()
{
if (Serial.available() >= 8) {
char buf[8];
unsigned hour, minute, second;
Serial.readBytes(buf, 8);
sscanf(buf, "%u %u %u", &hour, &minute, &second);
clock.fillByHMS(hour, minute, second);
clock.setTime();
#ifdef DEBUG
debug_clock("Clock synchronized", hour, minute, second);
#endif
}
clock.getTime();
clock_ctl.readCtl();
#ifdef DEBUG
debug_clock("Clock", clock.hour, clock.minute, clock.second);
debug_clock("Alarm", clock_ctl.alarm_hour, clock_ctl.alarm_minute, 0);
Serial.print("Alarm.enabled=");
Serial.print(clock_ctl.alarm_enabled);
Serial.print("\n");
Serial.print("\n");
#endif
setNixieTime(clock.hour, clock.minute);
if (clock_ctl.alarm_enabled
&& clock.hour == clock_ctl.alarm_hour
&& clock.minute == clock_ctl.alarm_minute) {
ringer(1000);
} else {
delay(1000);
}
//delay(1000);
}
int clk_enable_test_case1(void)
{
struct clk *sio_clk = clk_get(NULL,"sio_clk");
struct clk *apb_pclk = clk_get(NULL,"apb_pclk");
int ret = 0;
ret = clk_enable(sio_clk);
if(ret){
clk_printf("can't enable sio_clk\n");
return CLK_TEST_ERROR;
}
ret = clk_enable(apb_pclk);
clk_disable(apb_pclk);
ret |= clk_round_rate(apb_pclk,100);
ret |= clk_set_rate(apb_pclk,100);
ret |= clk_set_parent(apb_pclk,sio_clk);
ret |= clk_status(apb_pclk);
debug_clock();
debug_clk_enable(30);
debug_clk_disable(30);
debug_clk_set_rate(30,100);
debug_clk_get_rate(30);
debug_clk_set_parent(30,31);
debug_clk_status(30);
debug_clk_enable(14);
debug_clk_disable(14);
debug_clk_set_rate(14,100);
debug_clk_get_rate(14);
debug_clk_set_parent(14,15);
debug_clk_status(14);
if(ret)
return CLK_TEST_OK;
return CLK_TEST_OK;
}