void __init exynos_init_io(struct map_desc *mach_desc, int size)
{
struct map_desc *iodesc = exynos_iodesc;
int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
unsigned long root = of_get_flat_dt_root();
/* initialize the io descriptors we need for initialization */
if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
iodesc = exynos5440_iodesc;
iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
}
#endif
debug_ll_io_init();
iotable_init(iodesc, iodesc_sz);
if (mach_desc)
iotable_init(mach_desc, size);
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
/* TO support Watch dog reset */
wdt_reset_init();
/* Setup platform-specific resume code */
s5p_resume_cpu_id = samsung_cpu_id;
plat_cpu_resume = s3c_cpu_resume;
}
static void __init rk3288_dt_map_io(void)
{
iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
debug_ll_io_init();
usb_uart_init();
rockchip_soc_id = ROCKCHIP_SOC_RK3288;
/* rkpwm is used instead of old pwm */
writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
/* disable address remap */
writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
/* enable timer7 for core */
writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
dsb();
writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
dsb();
writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
dsb();
rk3288_boot_mode_init();
}
static void __init imx6q_map_io(void)
{
debug_ll_io_init();
imx_scu_map_io();
imx6_pm_map_io();
#ifdef CONFIG_CPU_FREQ
imx_busfreq_map_io();
#endif
}
static void __init s3c64xx_dt_map_io(void)
{
debug_ll_io_init();
iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
s3c64xx_init_cpu();
if (!soc_is_s3c64xx())
panic("SoC is not S3C64xx!");
}
static void __init rk3188_dt_map_io(void)
{
iotable_init(rk3188_io_desc, ARRAY_SIZE(rk3188_io_desc));
debug_ll_io_init();
usb_uart_init();
rockchip_soc_id = ROCKCHIP_SOC_RK3188;
if (readl_relaxed(RK_ROM_VIRT + 0x27f0) == 0x33313042
&& readl_relaxed(RK_ROM_VIRT + 0x27f4) == 0x32303133
&& readl_relaxed(RK_ROM_VIRT + 0x27f8) == 0x30313331
&& readl_relaxed(RK_ROM_VIRT + 0x27fc) == 0x56313031)
rockchip_soc_id = ROCKCHIP_SOC_RK3188PLUS;
/* rki2c is used instead of old i2c */
writel_relaxed(0xF800F800, RK_GRF_VIRT + RK3188_GRF_SOC_CON1);
rk3188_boot_mode_init();
}
static void __init rk3036_dt_map_io(void)
{
rockchip_soc_id = ROCKCHIP_SOC_RK3036;
iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
debug_ll_io_init();
usb_uart_init();
/* enable timer5 for core */
writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
dsb();
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
dsb();
writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
dsb();
rk3036_boot_mode_init();
}
static void __init rk3288_dt_map_io(void)
{
u32 v;
rockchip_soc_id = ROCKCHIP_SOC_RK3288;
iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
debug_ll_io_init();
usb_uart_init();
/* pmu reset by second global soft reset */
v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
v &= ~(3 << 2);
v |= 1 << 2;
writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
/* rkpwm is used instead of old pwm */
writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
/* disable address remap */
#ifndef CONFIG_ARM_TRUSTZONE
writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
#endif
/* enable timer7 for core */
writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
dsb();
writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
dsb();
writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
dsb();
/* power up/down GPU domain wait 1us */
writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);
rk3288_boot_mode_init();
#ifndef CONFIG_ARM_TRUSTZONE
rockchip_efuse_init();
#endif
}
void __init r8a7779_map_io(void)
{
debug_ll_io_init();
iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
}
static void __init sh73a0_map_io(void)
{
debug_ll_io_init();
iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
}
void __init tegra_map_common_io(void)
{
debug_ll_io_init();
iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
}
static void __init hi3620_map_io(void)
{
debug_ll_io_init();
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static void __init imx6sl_map_io(void)
{
debug_ll_io_init();
imx6_pm_map_io();
imx6_busfreq_map_io();
}
static void __init u8500_map_io(void)
{
debug_ll_io_init();
ux500_setup_id();
}
void __init ox820_map_common_io(void)
{
debug_ll_io_init();
iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
}
static void __init imx6q_map_io(void)
{
debug_ll_io_init();
imx_scu_map_io();
}
static void __init imx7d_map_io(void)
{
debug_ll_io_init();
imx7_pm_map_io();
imx_busfreq_map_io();
}
void __init pxa_map_io(void)
{
debug_ll_io_init();
iotable_init(ARRAY_AND_SIZE(common_io_desc));
}
