Exemple #1
0
// Read a single character from the input queue
static int
serial_getchar ()
{
	while (1)
	{
		DISABLE_INTERRUPTS
		if (!queue_is_empty (&g_rx_queue))
			break;

		ENABLE_INTERRUPTS
		delay_loop_ms (1);
	}

	int val = queue_read (&g_rx_queue);
	ENABLE_INTERRUPTS
	return val;
}
Exemple #2
0
/********************************************************************
 * INITIALIZATION
 * ******************************************************************/
void ENC2_Init(void) {

	debug_entry;
	
    //Set default bank
    currentBank = 0;

   	init_SPI2();

   	DeassertChipSelect_2();
	ENCX24J600_Reset();
	delay_loop_ms (100);
	ENCX24J600_Unreset ();

    // Perform a reliable reset
    ENC2_SendSystemReset();

    // Initialize RX tracking variables and other control state flags
    nextPacketPointer = RXSTART;

    // Set up TX/RX/UDA buffer addresses
    ENC2_WriteReg(ETXST, TXSTART);
    ENC2_WriteReg(ERXST, RXSTART);
    ENC2_WriteReg(ERXTAIL, RAMSIZE - 2);
    ENC2_WriteReg(EUDAST, USSTART);
    ENC2_WriteReg(EUDAND, USEND);

    // If promiscuous mode is set, than allow accept all packets
#ifdef PROMISCUOUS_MODE
    ENC2_WriteReg(ERXFCON, (ERXFCON_CRCEN | ERXFCON_RUNTEN | ERXFCON_UCEN | ERXFCON_NOTMEEN | ERXFCON_MCEN));
    dd
#endif

    // Set PHY Auto-negotiation to support 10BaseT Half duplex,
    // 10BaseT Full duplex, 100BaseTX Half Duplex, 100BaseTX Full Duplex,
    // and symmetric PAUSE capability
    ENC2_WritePHYReg(PHANA, PHANA_ADPAUS0 | PHANA_AD10FD | PHANA_AD10 | PHANA_AD100FD | PHANA_AD100 | PHANA_ADIEEE0);

    // Enable RX packet reception
    ENC2_BFSReg(ECON1, ECON1_RXEN);

	// KUKU, supaya GPIO aktif untuk deteck packet 
    ENC2_WriteReg(EIE, EIE_INTIE | EIE_LINKIE | EIE_PKTIE | EIE_TXABTIE | EIE_RXABTIE);

    debug_leave;
}
Exemple #3
0
// Write a single character to the output queue
static void
serial_putchar (char c)
{
	while (1)
	{
		DISABLE_INTERRUPTS
		if (!queue_is_full (&g_tx_queue))
			break;

		ENABLE_INTERRUPTS
		delay_loop_ms (1);
	}

	// Send straight away if we may
	if (queue_is_empty (&g_tx_queue) && !U1STAbits.UTXBF)
		U1TXREG = c;
	else
		queue_write (&g_tx_queue, c);
	ENABLE_INTERRUPTS
}