static int stm32_startup(struct uart_port *port) { struct stm32_port *stm32_port = to_stm32_port(port); struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; struct stm32_usart_config *cfg = &stm32_port->info->cfg; const char *name = to_platform_device(port->dev)->name; u32 val; int ret; ret = request_threaded_irq(port->irq, stm32_interrupt, stm32_threaded_interrupt, IRQF_NO_SUSPEND, name, port); if (ret) return ret; if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { ret = dev_pm_set_dedicated_wake_irq(port->dev, stm32_port->wakeirq); if (ret) { free_irq(port->irq, port); return ret; } } val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; if (stm32_port->fifoen) val |= USART_CR1_FIFOEN; stm32_set_bits(port, ofs->cr1, val); return 0; }
static int serial_omap_startup(struct uart_port *port) { struct uart_omap_port *up = to_uart_omap_port(port); unsigned long flags = 0; int retval; /* * Allocate the IRQ */ retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, up->name, up); if (retval) return retval; /* Optional wake-up IRQ */ if (up->wakeirq) { retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); if (retval) { free_irq(up->port.irq, up); return retval; } } dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); pm_runtime_get_sync(up->dev); /* * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ serial_omap_clear_fifos(up); /* * Clear the interrupt registers. */ (void) serial_in(up, UART_LSR); if (serial_in(up, UART_LSR) & UART_LSR_DR) (void) serial_in(up, UART_RX); (void) serial_in(up, UART_IIR); (void) serial_in(up, UART_MSR); /* * Now, initialize the UART */ serial_out(up, UART_LCR, UART_LCR_WLEN8); spin_lock_irqsave(&up->port.lock, flags); /* * Most PC uarts need OUT2 raised to enable interrupts. */ up->port.mctrl |= TIOCM_OUT2; serial_omap_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); up->msr_saved_flags = 0; /* * Finally, enable interrupts. Note: Modem status interrupts * are set via set_termios(), which will be occurring imminently * anyway, so we don't enable them here. */ up->ier = UART_IER_RLSI | UART_IER_RDI; serial_out(up, UART_IER, up->ier); /* Enable module level wake up */ up->wer = OMAP_UART_WER_MOD_WKUP; if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) up->wer |= OMAP_UART_TX_WAKEUP_EN; serial_out(up, UART_OMAP_WER, up->wer); pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); up->port_activity = jiffies; return 0; }
static int stm32_ipcc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct stm32_ipcc *ipcc; struct resource *res; unsigned int i; int ret; u32 ip_ver; static const char * const irq_name[] = {"rx", "tx"}; irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq}; if (!np) { dev_err(dev, "No DT found\n"); return -ENODEV; } ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL); if (!ipcc) return -ENOMEM; /* proc_id */ if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) { dev_err(dev, "Missing st,proc-id\n"); return -ENODEV; } if (ipcc->proc_id >= STM32_MAX_PROCS) { dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); return -EINVAL; } /* regs */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ipcc->reg_base = devm_ioremap_resource(dev, res); if (IS_ERR(ipcc->reg_base)) return PTR_ERR(ipcc->reg_base); ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; /* clock */ ipcc->clk = devm_clk_get(dev, NULL); if (IS_ERR(ipcc->clk)) return PTR_ERR(ipcc->clk); ret = clk_prepare_enable(ipcc->clk); if (ret) { dev_err(dev, "can not enable the clock\n"); return ret; } /* irq */ for (i = 0; i < IPCC_IRQ_NUM; i++) { ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]); if (ipcc->irqs[i] < 0) { if (ipcc->irqs[i] != -EPROBE_DEFER) dev_err(dev, "no IRQ specified %s\n", irq_name[i]); ret = ipcc->irqs[i]; goto err_clk; } ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL, irq_thread[i], IRQF_ONESHOT, dev_name(dev), ipcc); if (ret) { dev_err(dev, "failed to request irq %d (%d)\n", i, ret); goto err_clk; } } /* mask and enable rx/tx irq */ stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_MASK | TX_BIT_MASK); stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE); /* wakeup */ if (of_property_read_bool(np, "wakeup-source")) { ipcc->wkp = platform_get_irq_byname(pdev, "wakeup"); if (ipcc->wkp < 0) { if (ipcc->wkp != -EPROBE_DEFER) dev_err(dev, "could not get wakeup IRQ\n"); ret = ipcc->wkp; goto err_clk; } device_set_wakeup_capable(dev, true); ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp); if (ret) { dev_err(dev, "Failed to set wake up irq\n"); goto err_init_wkp; } } /* mailbox controller */ ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR); ipcc->n_chans &= IPCFGR_CHAN_MASK; ipcc->controller.dev = dev; ipcc->controller.txdone_irq = true; ipcc->controller.ops = &stm32_ipcc_ops; ipcc->controller.num_chans = ipcc->n_chans; ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, sizeof(*ipcc->controller.chans), GFP_KERNEL); if (!ipcc->controller.chans) { ret = -ENOMEM; goto err_irq_wkp; } for (i = 0; i < ipcc->controller.num_chans; i++) ipcc->controller.chans[i].con_priv = (void *)i; ret = devm_mbox_controller_register(dev, &ipcc->controller); if (ret) goto err_irq_wkp; platform_set_drvdata(pdev, ipcc); ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER); dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n", FIELD_GET(VER_MAJREV_MASK, ip_ver), FIELD_GET(VER_MINREV_MASK, ip_ver), ipcc->controller.num_chans, ipcc->proc_id); clk_disable_unprepare(ipcc->clk); return 0; err_irq_wkp: if (ipcc->wkp) dev_pm_clear_wake_irq(dev); err_init_wkp: device_init_wakeup(dev, false); err_clk: clk_disable_unprepare(ipcc->clk); return ret; }
static int omap_8250_startup(struct uart_port *port) { struct uart_8250_port *up = up_to_u8250p(port); struct omap8250_priv *priv = port->private_data; int ret; if (priv->wakeirq) { ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); if (ret) return ret; } pm_runtime_get_sync(port->dev); up->mcr = 0; serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_out(up, UART_LCR, UART_LCR_WLEN8); up->lsr_saved_flags = 0; up->msr_saved_flags = 0; /* Disable DMA for console UART */ if (uart_console(port)) up->dma = NULL; if (up->dma) { ret = serial8250_request_dma(up); if (ret) { dev_warn_ratelimited(port->dev, "failed to request DMA\n"); up->dma = NULL; } } ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, dev_name(port->dev), port); if (ret < 0) goto err; up->ier = UART_IER_RLSI | UART_IER_RDI; serial_out(up, UART_IER, up->ier); #ifdef CONFIG_PM up->capabilities |= UART_CAP_RPM; #endif /* Enable module level wake up */ priv->wer = OMAP_UART_WER_MOD_WKUP; if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) priv->wer |= OMAP_UART_TX_WAKEUP_EN; serial_out(up, UART_OMAP_WER, priv->wer); if (up->dma) up->dma->rx_dma(up); pm_runtime_mark_last_busy(port->dev); pm_runtime_put_autosuspend(port->dev); return 0; err: pm_runtime_mark_last_busy(port->dev); pm_runtime_put_autosuspend(port->dev); dev_pm_clear_wake_irq(port->dev); return ret; }