static int sh_tmu_enable(struct sh_tmu_channel *ch) { if (ch->enable_count++ > 0) return 0; pm_runtime_get_sync(&ch->tmu->pdev->dev); dev_pm_syscore_device(&ch->tmu->pdev->dev, true); return __sh_tmu_enable(ch); }
static int sh_tmu_enable(struct sh_tmu_priv *p) { if (p->enable_count++ > 0) return 0; pm_runtime_get_sync(&p->pdev->dev); dev_pm_syscore_device(&p->pdev->dev, true); return __sh_tmu_enable(p); }
static void sh_tmu_disable(struct sh_tmu_channel *ch) { if (WARN_ON(ch->enable_count == 0)) return; if (--ch->enable_count > 0) return; __sh_tmu_disable(ch); dev_pm_syscore_device(&ch->tmu->pdev->dev, false); pm_runtime_put(&ch->tmu->pdev->dev); }
static void sh_tmu_disable(struct sh_tmu_priv *p) { if (WARN_ON(p->enable_count == 0)) return; if (--p->enable_count > 0) return; __sh_tmu_disable(p); dev_pm_syscore_device(&p->pdev->dev, false); pm_runtime_put(&p->pdev->dev); }
static void sh_cmt_disable(struct sh_cmt_priv *p) { /* disable channel */ sh_cmt_start_stop_ch(p, 0); /* disable interrupts in CMT block */ sh_cmt_write_cmcsr(p, 0); /* stop clock */ clk_disable(p->clk); dev_pm_syscore_device(&p->pdev->dev, false); pm_runtime_put(&p->pdev->dev); }
static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) { int k, ret; pm_runtime_get_sync(&p->pdev->dev); dev_pm_syscore_device(&p->pdev->dev, true); /* enable clock */ ret = clk_enable(p->clk); if (ret) { dev_err(&p->pdev->dev, "cannot enable clock\n"); goto err0; } /* make sure channel is disabled */ sh_cmt_start_stop_ch(p, 0); /* configure channel, periodic mode and maximum timeout */ if (p->width == 16) { *rate = clk_get_rate(p->clk) / 512; sh_cmt_write_cmcsr(p, 0x43); } else { *rate = clk_get_rate(p->clk) / 8; sh_cmt_write_cmcsr(p, 0x01a4); } sh_cmt_write_cmcor(p, 0xffffffff); sh_cmt_write_cmcnt(p, 0); /* * According to the sh73a0 user's manual, as CMCNT can be operated * only by the RCLK (Pseudo 32 KHz), there's one restriction on * modifying CMCNT register; two RCLK cycles are necessary before * this register is either read or any modification of the value * it holds is reflected in the LSI's actual operation. * * While at it, we're supposed to clear out the CMCNT as of this * moment, so make sure it's processed properly here. This will * take RCLKx2 at maximum. */ for (k = 0; k < 100; k++) { if (!sh_cmt_read_cmcnt(p)) break; udelay(1); } if (sh_cmt_read_cmcnt(p)) { dev_err(&p->pdev->dev, "cannot clear CMCNT\n"); ret = -ETIMEDOUT; goto err1; } /* enable channel */ sh_cmt_start_stop_ch(p, 1); return 0; err1: /* stop clock */ clk_disable(p->clk); err0: return ret; }