static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
struct clk clk;
struct resource res;
int ret;
data = (void *)dev_get_driver_data(dev);
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
denali->ecc_caps = data->ecc_caps;
}
denali->dev = dev;
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_enable(&clk);
if (ret)
return ret;
denali->clk_x_rate = clk_get_rate(&clk);
return denali_init(denali);
}
static int mtk_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct resource res_reg, res_mem;
struct mtk_qspi_platdata *plat = bus->platdata;
int ret;
ret = dev_read_resource_byname(bus, "reg_base", &res_reg);
if (ret) {
debug("can't get reg_base resource(ret = %d)\n", ret);
return -ENOMEM;
}
ret = dev_read_resource_byname(bus, "mem_base", &res_mem);
if (ret) {
debug("can't get map_base resource(ret = %d)\n", ret);
return -ENOMEM;
}
plat->mem_base = res_mem.start;
plat->reg_base = res_reg.start;
return 0;
}
static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
const struct denali_dt_data *data;
struct clk clk, clk_x, clk_ecc;
struct resource res;
int ret;
data = (void *)dev_get_driver_data(dev);
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
denali->ecc_caps = data->ecc_caps;
}
denali->dev = dev;
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_name(dev, "nand", &clk);
if (ret)
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_get_by_name(dev, "nand_x", &clk_x);
if (ret)
clk_x.dev = NULL;
ret = clk_get_by_name(dev, "ecc", &clk_ecc);
if (ret)
clk_ecc.dev = NULL;
ret = clk_enable(&clk);
if (ret)
return ret;
if (clk_x.dev) {
ret = clk_enable(&clk_x);
if (ret)
return ret;
}
if (clk_ecc.dev) {
ret = clk_enable(&clk_ecc);
if (ret)
return ret;
}
if (clk_x.dev) {
denali->clk_rate = clk_get_rate(&clk);
denali->clk_x_rate = clk_get_rate(&clk_x);
} else {
/*
* Hardcode the clock rates for the backward compatibility.
* This works for both SOCFPGA and UniPhier.
*/
dev_notice(dev,
"necessary clock is missing. default clock rates are used.\n");
denali->clk_rate = 50000000;
denali->clk_x_rate = 200000000;
}
ret = reset_get_bulk(dev, &denali->resets);
if (ret)
dev_warn(dev, "Can't get reset: %d\n", ret);
else
reset_deassert_bulk(&denali->resets);
return denali_init(denali);
}
static int stm32_qspi_probe(struct udevice *bus)
{
struct stm32_qspi_priv *priv = dev_get_priv(bus);
struct resource res;
struct clk clk;
struct reset_ctl reset_ctl;
int ret;
ret = dev_read_resource_byname(bus, "qspi", &res);
if (ret) {
dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
return ret;
}
priv->regs = (struct stm32_qspi_regs *)res.start;
ret = dev_read_resource_byname(bus, "qspi_mm", &res);
if (ret) {
dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
return ret;
}
priv->mm_base = (void __iomem *)res.start;
priv->mm_size = resource_size(&res);
if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
return -EINVAL;
debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
__func__, priv->regs, priv->mm_base, priv->mm_size);
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
priv->clock_rate = clk_get_rate(&clk);
if (priv->clock_rate < 0) {
clk_disable(&clk);
return priv->clock_rate;
}
ret = reset_get_by_index(bus, 0, &reset_ctl);
if (ret) {
if (ret != -ENOENT) {
dev_err(bus, "failed to get reset\n");
clk_disable(&clk);
return ret;
}
} else {
/* Reset QSPI controller */
reset_assert(&reset_ctl);
udelay(2);
reset_deassert(&reset_ctl);
}
priv->cs_used = -1;
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
/* Set dcr fsize to max address */
setbits_le32(&priv->regs->dcr,
STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
return 0;
}
