static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct eth_sandbox_raw_priv *priv = dev_get_priv(dev); const char *ifname; u32 local; int ret; pdata->iobase = dev_read_addr(dev); ifname = dev_read_string(dev, "host-raw-interface"); if (ifname) { strncpy(priv->host_ifname, ifname, IFNAMSIZ); printf(": Using %s from DT\n", priv->host_ifname); } if (dev_read_u32(dev, "host-raw-interface-idx", &priv->host_ifindex) < 0) { priv->host_ifindex = 0; } else { ret = sandbox_eth_raw_os_idx_to_name(priv); if (ret < 0) return ret; printf(": Using interface index %d from DT (%s)\n", priv->host_ifindex, priv->host_ifname); } local = sandbox_eth_raw_os_is_local(priv->host_ifname); if (local < 0) return local; priv->local = local; return 0; }
static int ftgmac100_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct ftgmac100_data *priv = dev_get_priv(dev); const char *phy_mode; pdata->iobase = devfdt_get_addr(dev); pdata->phy_interface = -1; phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); return -EINVAL; } pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); } else { priv->rxdes0_edorr_mask = BIT(15); priv->txdes0_edotr_mask = BIT(15); } return clk_get_bulk(dev, &priv->clks); }
static int sandbox_flash_ofdata_to_platdata(struct udevice *dev) { struct sandbox_flash_plat *plat = dev_get_platdata(dev); plat->pathname = dev_read_string(dev, "sandbox,filepath"); return 0; }
static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); uc_priv->gpio_count = 2; uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); if (uc_priv->bank_name == NULL) uc_priv->bank_name = "pm8916_key"; return 0; }
static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0); uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); if (uc_priv->bank_name == NULL) uc_priv->bank_name = "pm8916"; return 0; }
static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) { struct ddr_info *priv = dev_get_priv(dev); int ret, idx; struct clk axidcg; struct stm32mp1_ddr_config config; #define PARAM(x, y) \ { x,\ offsetof(struct stm32mp1_ddr_config, y),\ sizeof(config.y) / sizeof(u32)} #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) const struct { const char *name; /* name in DT */ const u32 offset; /* offset in config struct */ const u32 size; /* size of parameters */ } param[] = { CTL_PARAM(reg), CTL_PARAM(timing), CTL_PARAM(map), CTL_PARAM(perf), PHY_PARAM(reg), PHY_PARAM(timing), PHY_PARAM(cal) }; config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); config.info.size = dev_read_u32_default(dev, "st,mem-size", 0); config.info.name = dev_read_string(dev, "st,mem-name"); if (!config.info.name) { debug("%s: no st,mem-name\n", __func__); return -EINVAL; } printf("RAM: %s\n", config.info.name); for (idx = 0; idx < ARRAY_SIZE(param); idx++) { ret = dev_read_u32_array(dev, param[idx].name, (void *)((u32)&config + param[idx].offset), param[idx].size); debug("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); if (ret) { pr_err("%s: Cannot read %s\n", __func__, param[idx].name); return -EINVAL; } } ret = clk_get_by_name(dev, "axidcg", &axidcg); if (ret) { debug("%s: Cannot found axidcg\n", __func__); return -EINVAL; } clk_disable(&axidcg); /* disable clock gating during init */ stm32mp1_ddr_init(priv, &config); clk_enable(&axidcg); /* enable clock gating */ /* check size */ debug("%s : get_ram_size(%x, %x)\n", __func__, (u32)priv->info.base, (u32)STM32_DDR_SIZE); priv->info.size = get_ram_size((long *)priv->info.base, STM32_DDR_SIZE); debug("%s : %x\n", __func__, (u32)priv->info.size); /* check memory access for all memory */ if (config.info.size != priv->info.size) { printf("DDR invalid size : 0x%x, expected 0x%x\n", priv->info.size, config.info.size); return -EINVAL; } return 0; }
static int gpio_stm32_probe(struct udevice *dev) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct clk clk; fdt_addr_t addr; int ret; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->regs = (struct stm32_gpio_regs *)addr; #ifndef CONFIG_SPL_BUILD struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct ofnode_phandle_args args; const char *name; int i; name = dev_read_string(dev, "st,bank-name"); if (!name) return -EINVAL; uc_priv->bank_name = name; i = 0; ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args); if (ret == -ENOENT) { uc_priv->gpio_count = STM32_GPIOS_PER_BANK; priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0); } while (ret != -ENOENT) { priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1, args.args[0]); uc_priv->gpio_count += args.args[2]; ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, ++i, &args); } dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n", (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count, priv->gpio_range); #endif ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; ret = clk_enable(&clk); if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } debug("clock enabled for device %s\n", dev->name); return 0; }