void dfll_enable_closed_loop(const struct dfll_config *cfg, unsigned int dfll_id) { irqflags_t flags; /* Enable the reference clock */ genclk_enable(&cfg->ref_cfg, 0); /* * Enable the DFLL first, but don't wait for the DFLL0RDY bit * because if the DFLL has been disabled before, the DFLL0RDY * bit stays cleared until it is re-enabled. */ flags = cpu_irq_save(); AVR32_SCIF.unlock = ( AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET ) | AVR32_SCIF_DFLL0CONF; AVR32_SCIF.dfll0conf = 1U << AVR32_SCIF_DFLL0CONF_EN; cpu_irq_restore(flags); /* * Then, configure the DFLL, taking care to wait for the * DFLL0RDY bit before every step. */ dfll_write_reg(DFLL0STEP, cfg->step); #if AVR32_SCIF_H_VERSION < 110 dfll_write_reg(DFLL0FMUL, cfg->mul); #else dfll_write_reg(DFLL0MUL, cfg->mul); #endif dfll_write_reg(DFLL0SSG, cfg->ssg); dfll_write_reg(DFLL0CONF, cfg->conf | (1U << AVR32_SCIF_DFLL0CONF_EN)); }
void dfll_enable_closed_loop(const struct dfll_config *cfg, uint32_t dfll_id) { irqflags_t flags; UNUSED(dfll_id); /* Enable the reference clock */ genclk_enable(&cfg->ref_cfg, 0); /* * Enable the DFLL first, but don't wait for the DFLL0RDY bit * because if the DFLL has been disabled before, the DFLL0RDY * bit stays cleared until it is re-enabled. */ flags = cpu_irq_save(); SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAUL) | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_DFLL0CONF - (uint32_t)SCIF); SCIF->SCIF_DFLL0CONF = SCIF_DFLL0CONF_EN; cpu_irq_restore(flags); /* * Then, configure the DFLL, taking care to wait for the * DFLL0RDY bit before every step. */ dfll_write_reg(DFLL0STEP, cfg->step); dfll_write_reg(DFLL0MUL, cfg->mul); dfll_write_reg(DFLL0SSG, cfg->ssg); dfll_write_reg(DFLL0CONF, cfg->conf | SCIF_DFLL0CONF_EN); }
void dfll_disable_open_loop(unsigned int dfll_id) { /* * First, reduce the frequency to the lowest setting, then * disable the DFLL. */ dfll_write_reg(DFLL0CONF, 1U << AVR32_SCIF_DFLL0CONF_EN); dfll_write_reg(DFLL0CONF, 0); }
void dfll_disable_closed_loop(unsigned int dfll_id) { /* * First, reduce the frequency to the lowest setting, then * disable the DFLL. */ dfll_write_reg(DFLL0CONF, 1U << AVR32_SCIF_DFLL0CONF_EN); dfll_write_reg(DFLL0CONF, 0); /* Finally, stop the reference clock */ genclk_disable(0); }
void dfll_enable_open_loop(const struct dfll_config *cfg, unsigned int dfll_id) { irqflags_t flags; /* First, enable the DFLL, then configure it */ flags = cpu_irq_save(); AVR32_SCIF.unlock = ( AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET) | AVR32_SCIF_DFLL0CONF; AVR32_SCIF.dfll0conf = 1U << AVR32_SCIF_DFLL0CONF_EN; cpu_irq_restore(flags); dfll_write_reg(DFLL0CONF, cfg->conf | (1U << AVR32_SCIF_DFLL0CONF_EN)); dfll_write_reg(DFLL0SSG, cfg->ssg); }
void dfll_enable_open_loop(const struct dfll_config *cfg, uint32_t dfll_id) { irqflags_t flags; UNUSED(dfll_id); /* First, enable the DFLL, then configure it */ flags = cpu_irq_save(); SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAUL) | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_DFLL0CONF - (uint32_t)SCIF); SCIF->SCIF_DFLL0CONF = SCIF_DFLL0CONF_EN; cpu_irq_restore(flags); dfll_write_reg(DFLL0CONF, cfg->conf | SCIF_DFLL0CONF_EN); dfll_write_reg(DFLL0MUL, cfg->mul); dfll_write_reg(DFLL0VAL, cfg->val); dfll_write_reg(DFLL0SSG, cfg->ssg); }
void dfll_disable_open_loop(uint32_t dfll_id) { UNUSED(dfll_id); /* First, disable the DFLL. */ // Do a sync before reading a dfll conf register SCIF->SCIF_DFLL0SYNC = SCIF_DFLL0SYNC_SYNC; while (!(SCIF->SCIF_PCLKSR & SCIF_PCLKSR_DFLL0RDY)); uint32_t conf = SCIF->SCIF_DFLL0CONF; conf &= ~SCIF_DFLL0CONF_EN; dfll_write_reg(DFLL0CONF, conf); /* Finally, stop the reference clock */ genclk_disable(0); }