void musb_platform_disable(struct musb *musb)
{
printk("%s, %d, %d\n", __func__, mtk_usb_power, musb->power);
if(musb->power == false)
return;
if (platform_init_first) {
DBG(0,"usb init first\n\r");
musb->is_host = false;
platform_init_first = false;
}
if (mtk_usb_power) {
if (down_interruptible(&power_clock_lock))
xlog_printk(ANDROID_LOG_ERROR, "USB20", "%s: busy, Couldn't get power_clock_lock\n" \
, __func__);
#ifndef CONFIG_MT6575T_FPGA
usb_phy_savecurrent();
hwPowerDown(MT65XX_POWER_LDO_VUSB,"VUSB_LDO");
disable_pll(MT65XX_UPLL,"USB_PLL");
printk("%s, disable VUSB and UPLL before disconnect\n", __func__);
#endif
mtk_usb_power = false;
up(&power_clock_lock);
}
musb->power = false;
}
void mt65xx_usb11_phy_savecurrent(void)
{
INFO("mt65xx_usb11_phy_savecurrent++\r\n");
#if 0
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_SESSEND);
USB11PHY_CLR8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
USB11PHY_SET8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
USB11PHY_CLR8(U1PHYCR1+3, RG_USB11_EN_FS_LS_RCV | RG_USB11_EN_FS_LS_TX);
#endif
//4 1. swtich to USB function. (system register, force ip into usb mode.
USB11PHY_CLR8(0x6b, 0x04);
USB11PHY_CLR8(0x6e, 0x01);
//4 2. release force suspendm.
USB11PHY_CLR8(0x6a, 0x04);
//4 3. RG_DPPULLDOWN./RG_DMPULLDOWN.
USB11PHY_SET8(0x68, 0xc0);
//4 4. RG_XCVRSEL[1:0] =2'b01.
USB11PHY_CLR8(0x68, 0x30);
USB11PHY_SET8(0x68, 0x10);
//4 5. RG_TERMSEL = 1'b1
USB11PHY_SET8(0x68, 0x04);
//4 6. RG_DATAIN[3:0]=4'b0000
USB11PHY_CLR8(0x69, 0x3c);
//4 7.force_dp_pulldown, force_dm_pulldown, force_xcversel,force_termsel.
USB11PHY_SET8(0x6a, 0xba);
//4 8.RG_USB20_BC11_SW_EN 1'b0
USB11PHY_CLR8(0x1a, 0x80);
//4 9.RG_USB20_OTG_VBUSSCMP_EN 1'b0
USB11PHY_CLR8(0x1a, 0x10);
//4 10. delay 800us.
udelay(800);
//4 11. rg_usb20_pll_stable = 1
USB11PHY_SET8(0x63, 0x02);
udelay(1);
//4 12. force suspendm = 1.
USB11PHY_SET8(0x6a, 0x04);
USB11PHY_CLR8(0x6C, 0x2C);
USB11PHY_SET8(0x6C, 0x10);
USB11PHY_CLR8(0x6D, 0x3C);
//4 13. wait 1us
udelay(1);
//4 14. turn off internal 48Mhz PLL.
disable_pll(UNIVPLL, "USB11");
}
void disp_set_pll(unsigned int freq)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
if (freq == freq_last)
return;
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 182) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_182MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_182MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 364) {
clkmux_sel(MT_MUX_MM, 1, DISP_CLOCK_USER_NAME);
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
}
void mt65xx_usb11_phy_savecurrent(void)
{
INFO("mt65xx_usb11_phy_savecurrent++\r\n");
USB11PHY_SET8(U1PHTCR2+3, force_usb11_avalid | force_usb11_sessend | force_usb11_vbusvalid);
USB11PHY_CLR8(U1PHTCR2+2, RG_USB11_AVALID | RG_USB11_VBUSVALID);
USB11PHY_SET8(U1PHTCR2+2, RG_USB11_SESSEND);
USB11PHY_CLR8(U1PHYCR0+1, RG_USB11_FSLS_ENBGRI);
USB11PHY_SET8(U1PHYCR1+2, force_usb11_en_fs_ls_rcv | force_usb11_en_fs_ls_tx);
USB11PHY_CLR8(U1PHYCR1+3, RG_USB11_EN_FS_LS_RCV | RG_USB11_EN_FS_LS_TX);
disable_pll(MT65XX_UPLL, "USB11");
}
DPI_STATUS DPI_PowerOff()
{
if (s_isDpiPowerOn)
{
int ret = TRUE;
_BackupDPIRegisters();
disable_pll(LVDSPLL, "dpi0");
#if 1
ret = disable_clock(MT_CG_DISP1_DPI0, "DPI");
if(1 == ret)
{
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DPI", "power manager API return FALSE\n");
}
#endif
s_isDpiPowerOn = FALSE;
}
return DPI_STATUS_OK;
}
TVE_STATUS TVE_PowerOff()
{
if (s_isTvePowerOn)
{
BOOL ret = TRUE;
_BackupTVERegisters();
#if 1
ret = disable_pll(MT65XX_TVDDS, "TVE");
ASSERT(!ret);
#endif
ret = disable_clock(MT65XX_PDN_MM_TVE, "TVE");
ASSERT(!ret);
s_isTvePowerOn = FALSE;
}
return TVE_STATUS_OK;
}
DPI_STATUS DPI_PowerOff()
{
#ifndef CONFIG_MT6589_FPGA
if (s_isDpiPowerOn)
{
int ret = TRUE;
_BackupDPIRegisters();
disable_pll(LVDSPLL, "dpi0");
#if 0 // FIXME
ret = disable_clock(MT65XX_PDN_MM_DPI, "DPI");
if(1 == ret)
{
DISP_LOG_PRINT(ANDROID_LOG_ERROR, "DPI", "power manager API return FALSE\n");
}
#endif
s_isDpiPowerOn = FALSE;
}
#endif
return DPI_STATUS_OK;
}
void musb_platform_disable(struct musb *musb)
{
printk("%s, %d, %d\n", __func__, mtk_usb_power, musb->power);
if(musb->power == false)
return;
if(platform_init_first){
DBG(0,"usb init first\n\r");
musb->is_host = false;
platform_init_first = false;
}
if (mtk_usb_power) {
if (down_interruptible(&power_clock_lock))
xlog_printk(ANDROID_LOG_ERROR, "USB20", "%s: busy, Couldn't get power_clock_lock\n" \
, __func__);
//Modification for ALPS00408742
mtk_usb_power = false;
smp_mb();
//printk("%s, line %d: %d, %d, before savecurrent\n", __func__, __LINE__, mtk_usb_power, musb->power);
//Modification for ALPS00408742
usb_phy_savecurrent();
#ifndef CONFIG_MT6589_FPGA
disable_pll(UNIVPLL,"USB_PLL");
//printk("%s, disable VUSB and UPLL before disconnect\n", __func__);
#endif
mtk_usb_power = false;
//Modification for ALPS00408742
smp_mb();
//Modification for ALPS00408742
up(&power_clock_lock);
}
musb->power = false;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
// DSI_clk_HS_mode(1);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
#endif
DSI_clk_HS_mode(0);
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
// DSI_CHECK_RET(DSI_PowerOff());
DSI_PHY_clk_switch(0);
DSI_CHECK_RET(DSI_PowerOff());
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
} else {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(1);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
DSI_PHY_clk_switch(1);
#ifndef MT65XX_NEW_DISP
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
needStartDSI = true;
if(lcm_params->dsi.pll_select == 1)
{
ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
}
DSI_PHY_clk_setting(lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#endif
#endif
} else {
#ifndef BUILD_UBOOT
is_video_mode_running = false;
#ifndef MT65XX_NEW_DISP
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
#ifndef MT65XX_NEW_DISP
LCD_CHECK_RET(LCD_PowerOff());
DPI_CHECK_RET(DPI_PowerOff());
#endif
#if 1
DSI_lane0_ULP_mode(1);
DSI_clk_ULP_mode(1);
DSI_CHECK_RET(DSI_PowerOff());
#endif
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
if(lcm_params->dsi.pll_select == 1)
ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
}
}
return DISP_STATUS_OK;
}
unsigned int disp_set_pll_by_cmdq(unsigned int freq, void *cmdq_handle)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
unsigned int i = 0;
if (freq == freq_last)
/* return; */
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
cmdqRecWaitNoClear(cmdq_handle, CMDQ_EVENT_MUTEX0_STREAM_EOF);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
pll_cnt++;
/* set mux to 3 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else if (freq == 182) {
/*NOT USE*/
} else if (freq == 364) {
/* set mux to 1 by CMDQ */
DISP_REG_SET_PA(cmdq_handle, 0x10000048, 0x3000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000044, 0x1000000);
DISP_REG_SET_PA(cmdq_handle, 0x10000004, 8);
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
/* cmdqRecDumpCommand(cmdq_handle); */
cmdqRecFlush(cmdq_handle);
if (freq == 364) {
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
return 0; /* cmdqRecEstimateEommandExecTime(cmdq_handle); */
}
