static int32_t sprd_dsi_force_read(uint8_t command, uint8_t bytes_to_read, uint8_t * read_buffer)
{
int32_t iRtn = 0;
uint32_t reg_val, reg_val_1, reg_val_2;
iRtn = mipi_dsih_gen_rd_packet(&(dsi_ctx.dsi_inst), 0, 6, 0, command, bytes_to_read, read_buffer);
reg_val = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_PHY_STATUS);
#ifdef FB_DSIH_VERSION_1P21A
reg_val_1 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_INT_ST0);
reg_val_2 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_INT_ST1);
#else
reg_val_1 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST0);
reg_val_2 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST1);
#endif
if(0 != (reg_val & 0x2)){
printk("sprdfb: [%s] mipi read hang (0x%x)!\n", __FUNCTION__, reg_val);
dsi_ctx.status = 2;
iRtn = 0;
}
if(0 != (reg_val_1 & 0x701)){
printk("sprdfb: [%s] mipi read status error!(0x%x, 0x%x)\n", __FUNCTION__, reg_val_1, reg_val_2);
iRtn = 0;
}
if(0 == iRtn){
printk(KERN_ERR "sprdfb: [%s] return error (%d)\n", __FUNCTION__, iRtn);
return -1;
}
return 0;
}
static int32_t sprdfb_dsi_gen_read(uint8_t *param, uint16_t param_length, uint8_t bytes_to_read, uint8_t *read_buffer)
{
uint16_t result;
uint32_t reg_val, reg_val_1, reg_val_2;
result = mipi_dsih_gen_rd_cmd(&(dsi_ctx.dsi_inst), 0, param, param_length, bytes_to_read, read_buffer);
reg_val = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_PHY_STATUS);
#ifdef FB_DSIH_VERSION_1P21A
reg_val_1 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_INT_ST0);
reg_val_2 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_INT_ST1);
#else
reg_val_1 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST0);
reg_val_2 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST1);
#endif
if(0 != (reg_val & 0x2)){
printk("sprdfb: [%s] mipi read hang (0x%x)!\n", __FUNCTION__, reg_val);
dsi_ctx.status = 2;
result = 0;
}
if(0 != (reg_val_1 & 0x701)){
printk("sprdfb: [%s] mipi read status error!(0x%x, 0x%x)\n", __FUNCTION__, reg_val_1, reg_val_2);
result = 0;
}
if(0 == result){
printk(KERN_ERR "sprdfb: [%s] return error (%d)\n", __FUNCTION__, result);
return -1;
}
return 0;
}
static int32_t sprdfb_dsi_dcs_read(uint8_t command, uint8_t bytes_to_read, uint8_t *read_buffer)
{
uint16_t result;
uint32_t reg_val, reg_val_1, reg_val_2;
result = mipi_dsih_dcs_rd_cmd(&(dsi_ctx.dsi_inst), 0, command, bytes_to_read, read_buffer);
reg_val = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_PHY_STATUS);
reg_val_1 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST0);
reg_val_2 = dispc_glb_read(SPRD_MIPI_DSIC_BASE + R_DSI_HOST_ERROR_ST1);
if(0 != (reg_val & 0x2)){
printk("sprdfb: [%s] mipi read hang (0x%x)!\n", __FUNCTION__, reg_val);
dsi_ctx.status = 2;
result = 0;
}
if(0 != (reg_val_1 & 0x701)){
printk("sprdfb: [%s] mipi read status error!(0x%x, 0x%x)\n", __FUNCTION__, reg_val_1, reg_val_2);
result = 0;
}
if(0 == result){
printk(KERN_ERR "[DISP] sprdfb: [%s] return error (%d)\n", __FUNCTION__, result);
return -1;
}
return 0;
}
static void dsi_reset(void)
{
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x,BIT_DSI_SOFT_RST:%lx\n",DSI_AHB_SOFT_RST,BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
sci_glb_set(DSI_AHB_SOFT_RST, BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
udelay(10);
sci_glb_clr(DSI_AHB_SOFT_RST, BIT_DSI_SOFT_RST);
pr_debug("[DISP] sprdfb:DSI_AHB_SOFT_RST:%x \n",dispc_glb_read(DSI_AHB_SOFT_RST));
}
uint32_t sprdfb_get_chip_id(void)
{
uint32_t adie_chip_id = sci_get_chip_id();
if((adie_chip_id & 0xffff0000) < 0x50000000) {
printk("sprdfb: [%s], chip id 0x%08x is invalidate, try to get it by reading reg directly!\n", __FUNCTION__, adie_chip_id);
adie_chip_id = dispc_glb_read(SPRD_AONAPB_BASE+0xFC);
if((adie_chip_id & 0xffff0000) < 0x50000000) {
printk("sprdfb: [%s], chip id 0x%08x from reg is invalidate too!\n", __FUNCTION__, adie_chip_id);
}
}
printk("sprdfb: return chip id 0x%08x \n", adie_chip_id);
return adie_chip_id;
}
void dispc_print_clk(void)
{
u32 reg_val0, reg_val1, reg_val2;
reg_val0 = dispc_glb_read(SPRD_AONAPB_BASE + 0x4);
reg_val1 = dispc_glb_read(SPRD_AHB_BASE);
reg_val2 = dispc_glb_read(SPRD_APBREG_BASE);
pr_info("sprdfb:0x402e0004 = 0x%x 0x20d00000 = 0x%x 0x71300000 = 0x%x\n",
reg_val0, reg_val1, reg_val2);
reg_val0 = dispc_glb_read(SPRD_APBCKG_BASE + 0x34);
reg_val1 = dispc_glb_read(SPRD_APBCKG_BASE + 0x30);
reg_val2 = dispc_glb_read(SPRD_APBCKG_BASE + 0x2c);
pr_info("sprdfb:0x71200034 = 0x%x 0x71200030 = 0x%x 0x7120002c = 0x%x\n",
reg_val0, reg_val1, reg_val2);
}
void dsi_core_and_function(unsigned int addr,unsigned int data)
{
sci_glb_write(addr,(dispc_glb_read(addr) & data), 0xffffffff);
}
static uint32_t dsi_core_read_function(uint32_t addr, uint32_t offset)
{
return dispc_glb_read(addr + offset);
}