void
display_crtc_dpms(uint8 crtcID, int mode)
{
radeon_shared_info &info = *gInfo->shared_info;
switch (mode) {
case B_DPMS_ON:
TRACE("%s: crtc %" B_PRIu8 " dpms powerup\n", __func__, crtcID);
if (gDisplay[crtcID]->attached == false)
return;
display_crtc_power(crtcID, ATOM_ENABLE);
gDisplay[crtcID]->powered = true;
if (info.dceMajor >= 3)
display_crtc_memreq(crtcID, ATOM_ENABLE);
display_crtc_blank(crtcID, ATOM_BLANKING_OFF);
break;
case B_DPMS_STAND_BY:
case B_DPMS_SUSPEND:
case B_DPMS_OFF:
TRACE("%s: crtc %" B_PRIu8 " dpms powerdown\n", __func__, crtcID);
if (gDisplay[crtcID]->attached == false)
return;
if (gDisplay[crtcID]->powered == true)
display_crtc_blank(crtcID, ATOM_BLANKING);
if (info.dceMajor >= 3)
display_crtc_memreq(crtcID, ATOM_DISABLE);
display_crtc_power(crtcID, ATOM_DISABLE);
gDisplay[crtcID]->powered = false;
}
}
void
radeon_dpms_set(int mode)
{
radeon_shared_info &info = *gInfo->shared_info;
switch(mode) {
case B_DPMS_ON:
TRACE("%s: ON\n", __func__);
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
continue;
display_crtc_lock(id, ATOM_ENABLE);
display_crtc_power(id, ATOM_ENABLE);
if (info.dceMajor >= 3)
display_crtc_memreq(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_BLANKING_OFF);
display_crtc_lock(id, ATOM_DISABLE);
}
break;
case B_DPMS_STAND_BY:
case B_DPMS_SUSPEND:
case B_DPMS_OFF:
TRACE("%s: OFF\n", __func__);
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
continue;
display_crtc_lock(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_BLANKING);
if (info.dceMajor >= 3)
display_crtc_memreq(id, ATOM_DISABLE);
display_crtc_power(id, ATOM_DISABLE);
display_crtc_lock(id, ATOM_DISABLE);
}
break;
}
gInfo->dpms_mode = mode;
}
status_t
radeon_set_display_mode(display_mode *mode)
{
radeon_shared_info &info = *gInfo->shared_info;
// Set mode on each display
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
continue;
uint16 connectorIndex = gDisplay[id]->connectorIndex;
// *** encoder prep
encoder_output_lock(true);
encoder_dpms_set(id, gConnector[connectorIndex]->encoder.objectID,
B_DPMS_OFF);
encoder_assign_crtc(id);
// *** CRT controler prep
display_crtc_lock(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_BLANKING);
if (info.dceMajor >= 3)
display_crtc_memreq(id, ATOM_DISABLE);
display_crtc_power(id, ATOM_DISABLE);
// *** CRT controler mode set
// TODO: program SS
pll_set(ATOM_PPLL1, mode->timing.pixel_clock, id);
// TODO: check if ATOM_PPLL1 is used and use ATOM_PPLL2 if so
display_crtc_set_dtd(id, mode);
display_crtc_fb_set(id, mode);
// atombios_overscan_setup
display_crtc_scale(id, mode);
// *** encoder mode set
encoder_mode_set(id, mode->timing.pixel_clock);
// *** CRT controler commit
display_crtc_power(id, ATOM_ENABLE);
if (info.dceMajor >= 3)
display_crtc_memreq(id, ATOM_ENABLE);
display_crtc_blank(id, ATOM_BLANKING_OFF);
display_crtc_lock(id, ATOM_DISABLE);
// *** encoder commit
encoder_dpms_set(id, gConnector[connectorIndex]->encoder.objectID,
B_DPMS_ON);
encoder_output_lock(false);
}
// for debugging
TRACE("D1CRTC_STATUS Value: 0x%X\n", Read32(CRT, D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS));
TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D1CRTC_CONTROL));
TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D2CRTC_CONTROL));
TRACE("D1GRPH_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D1GRPH_ENABLE));
TRACE("D2GRPH_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D2GRPH_ENABLE));
TRACE("D1SCL_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D1SCL_SCALER_ENABLE));
TRACE("D2SCL_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D2SCL_SCALER_ENABLE));
TRACE("D1CRTC_BLANK_CONTROL Value: 0x%X\n",
Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL));
TRACE("D2CRTC_BLANK_CONTROL Value: 0x%X\n",
Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL));
return B_OK;
}
