static struct ppa_addr linear_to_generic_addr(struct nvm_dev *dev,
struct ppa_addr r)
{
struct ppa_addr l;
int secs, pgs, blks, luns;
sector_t ppa = r.ppa;
l.ppa = 0;
div_u64_rem(ppa, dev->sec_per_pg, &secs);
l.g.sec = secs;
sector_div(ppa, dev->sec_per_pg);
div_u64_rem(ppa, dev->pgs_per_blk, &pgs);
l.g.pg = pgs;
sector_div(ppa, dev->pgs_per_blk);
div_u64_rem(ppa, dev->blks_per_lun, &blks);
l.g.blk = blks;
sector_div(ppa, dev->blks_per_lun);
div_u64_rem(ppa, dev->luns_per_chnl, &luns);
l.g.lun = luns;
sector_div(ppa, dev->luns_per_chnl);
l.g.ch = ppa;
return l;
}
unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt)
{
int dev_num = block_dev->devnum;
int err = 0;
u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
if (!mmc)
return -1;
err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
block_dev->hwpart);
if (err < 0)
return -1;
/*
* We want to see if the requested start or total block count are
* unaligned. We discard the whole numbers and only care about the
* remainder.
*/
err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);
err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);
if (start_rem || blkcnt_rem)
printf("\n\nCaution! Your devices Erase group is 0x%x\n"
"The erase range would be change to "
"0x" LBAF "~0x" LBAF "\n\n",
mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
((start + blkcnt + mmc->erase_grp_size)
& ~(mmc->erase_grp_size - 1)) - 1);
while (blk < blkcnt) {
blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
mmc->erase_grp_size : (blkcnt - blk);
err = mmc_erase_t(mmc, start + blk, blk_r);
if (err)
break;
blk += blk_r;
/* Waiting for the ready status */
if (mmc_send_status(mmc, timeout))
return 0;
}
return blk;
}
static inline int sst_calc_tstamp(struct intel_sst_drv *ctx,
struct pcm_stream_info *info,
struct snd_pcm_substream *substream,
struct snd_sst_tstamp *fw_tstamp)
{
size_t delay_bytes, delay_frames;
size_t buffer_sz;
u32 pointer_bytes, pointer_samples;
dev_dbg(ctx->dev, "mrfld ring_buffer_counter %llu in bytes\n",
fw_tstamp->ring_buffer_counter);
dev_dbg(ctx->dev, "mrfld hardware_counter %llu in bytes\n",
fw_tstamp->hardware_counter);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
delay_bytes = (size_t) (fw_tstamp->ring_buffer_counter -
fw_tstamp->hardware_counter);
else
delay_bytes = (size_t) (fw_tstamp->hardware_counter -
fw_tstamp->ring_buffer_counter);
delay_frames = bytes_to_frames(substream->runtime, delay_bytes);
buffer_sz = snd_pcm_lib_buffer_bytes(substream);
div_u64_rem(fw_tstamp->ring_buffer_counter, buffer_sz, &pointer_bytes);
pointer_samples = bytes_to_samples(substream->runtime, pointer_bytes);
dev_dbg(ctx->dev, "pcm delay %zu in bytes\n", delay_bytes);
info->buffer_ptr = pointer_samples / substream->runtime->channels;
info->pcm_delay = delay_frames / substream->runtime->channels;
dev_dbg(ctx->dev, "buffer ptr %llu pcm_delay rep: %llu\n",
info->buffer_ptr, info->pcm_delay);
return 0;
}
static ssize_t show_pw20_wait_time(struct device *dev,
struct device_attribute *attr, char *buf)
{
u32 value;
u64 tb_cycle = 1;
u64 time;
unsigned int cpu = dev->id;
if (!pw20_wt) {
smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
value = (value & PWRMGTCR0_PW20_ENT) >>
PWRMGTCR0_PW20_ENT_SHIFT;
tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
/* convert ms to ns */
if (tb_ticks_per_usec > 1000) {
time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
} else {
u32 rem_us;
time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
&rem_us);
time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
}
} else {
static void do_test_sync_cmpxchg(void)
{
int ret;
unsigned long flags;
unsigned int i;
cycles_t time1, time2, time;
u32 rem;
local_irq_save(flags);
preempt_disable();
time1 = get_cycles();
for (i = 0; i < NR_LOOPS; i++) {
#ifdef CONFIG_X86_32
ret = sync_cmpxchg(&test_val, 0, 0);
#else
ret = cmpxchg(&test_val, 0, 0);
#endif
}
time2 = get_cycles();
local_irq_restore(flags);
preempt_enable();
time = time2 - time1;
printk(KERN_ALERT "test results: time for locked cmpxchg\n");
printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
printk(KERN_ALERT "total time: %llu\n", time);
time = div_u64_rem(time, NR_LOOPS, &rem);
printk(KERN_ALERT "-> locked cmpxchg takes %llu cycles\n", time);
printk(KERN_ALERT "test end\n");
}
static void do_testbaseline(void)
{
unsigned long flags;
unsigned int i;
cycles_t time1, time2, time;
u32 rem;
local_irq_save(flags);
preempt_disable();
time1 = get_cycles();
for (i = 0; i < NR_LOOPS; i++) {
asm volatile ("");
}
time2 = get_cycles();
local_irq_restore(flags);
preempt_enable();
time = time2 - time1;
printk(KERN_ALERT "test results: time for baseline\n");
printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
printk(KERN_ALERT "total time: %llu\n", time);
time = div_u64_rem(time, NR_LOOPS, &rem);
printk(KERN_ALERT "-> baseline takes %llu cycles\n", time);
printk(KERN_ALERT "test end\n");
}
static bool bl_map_stripe(struct pnfs_block_dev *dev, u64 offset,
struct pnfs_block_dev_map *map)
{
struct pnfs_block_dev *child;
u64 chunk;
u32 chunk_idx;
u64 disk_offset;
chunk = div_u64(offset, dev->chunk_size);
div_u64_rem(chunk, dev->nr_children, &chunk_idx);
if (chunk_idx > dev->nr_children) {
dprintk("%s: invalid chunk idx %d (%lld/%lld)\n",
__func__, chunk_idx, offset, dev->chunk_size);
/* error, should not happen */
return false;
}
/* truncate offset to the beginning of the stripe */
offset = chunk * dev->chunk_size;
/* disk offset of the stripe */
disk_offset = div_u64(offset, dev->nr_children);
child = &dev->children[chunk_idx];
child->map(child, disk_offset, map);
map->start += offset;
map->disk_offset += disk_offset;
map->len = dev->chunk_size;
return true;
}
static void do_test_inc(void)
{
int ret;
unsigned long flags;
unsigned int i;
cycles_t time1, time2, time;
u32 rem;
local_t loc_val;
local_irq_save(flags);
preempt_disable();
time1 = get_cycles();
for (i = 0; i < NR_LOOPS; i++) {
ret = local_add_return(10, &loc_val);
}
time2 = get_cycles();
local_irq_restore(flags);
preempt_enable();
time = time2 - time1;
printk(KERN_ALERT "test results: time for non locked add return\n");
printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
printk(KERN_ALERT "total time: %llu\n", time);
time = div_u64_rem(time, NR_LOOPS, &rem);
printk(KERN_ALERT "-> non locked add return takes %llu cycles\n", time);
printk(KERN_ALERT "test end\n");
}
/**
* ixgbe_ptp_enable_sdp
* @hw - the hardware private structure
* @shift - the clock shift for calculating nanoseconds
*
* this function enables the clock out feature on the sdp0 for the
* X540 device. It will create a 1second periodic output that can be
* used as the PPS (via an interrupt).
*
* It calculates when the systime will be on an exact second, and then
* aligns the start of the PPS signal to that value. The shift is
* necessary because it can change based on the link speed.
*/
static void ixgbe_ptp_enable_sdp(struct ixgbe_hw *hw, int shift)
{
u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh;
u64 clock_edge = 0;
u32 rem;
switch (hw->mac.type) {
case ixgbe_mac_X540:
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
/*
* enable the SDP0 pin as output, and connected to the native
* function for Timesync (ClockOut)
*/
esdp |= (IXGBE_ESDP_SDP0_DIR |
IXGBE_ESDP_SDP0_NATIVE);
/*
* enable the Clock Out feature on SDP0, and allow interrupts
* to occur when the pin changes
*/
tsauxc = (IXGBE_TSAUXC_EN_CLK |
IXGBE_TSAUXC_SYNCLK |
IXGBE_TSAUXC_SDP0_INT);
/* clock period (or pulse length) */
clktiml = (u32)(NSECS_PER_SEC << shift);
clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
/*
* account for the fact that we can't do u64 division
* with remainder, by converting the clock values into
* nanoseconds first
*/
clock_edge >>= shift;
div_u64_rem(clock_edge, NSECS_PER_SEC, &rem);
clock_edge += (NSECS_PER_SEC - rem);
clock_edge <<= shift;
/* specify the initial clock start time */
trgttiml = (u32)clock_edge;
trgttimh = (u32)(clock_edge >> 32);
IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_TIMESYNC);
break;
default:
break;
}
}
int trace_print_message(char* str, size_t size,
const void* msg, size_t msg_size, int cpu, u64 ts, void* user_data)
{
int result, result_total = 0;
const struct kedr_trace_message* msg_real =
(const struct kedr_trace_message*)msg;
// ts is time in nanoseconds since system starts
u32 sec, ms;
sec = div_u64_rem(ts, 1000000000, &ms);
ms /= 1000;
(void)user_data;
#define update_str(str, size, result) \
if(size <= result) { str += size; size = 0; } \
else{ str += result; size -= result; }
result = snprintf(str, size, "%s-%d\t[%.03d]\t%lu.%.06u:\t",
msg_real->command, msg_real->pid,
cpu, (unsigned long)sec, (unsigned)ms);
result_total += result;
update_str(str, size, result);
result = msg_real->pp(str,
size, msg_real->data);
result_total += result;
update_str(str, size, result);
result = snprintf(str, size, "\n");
result_total += result;
#undef update_str
return result_total;
}
static void do_test_int(void)
{
unsigned long flags;
unsigned int i;
cycles_t time1, time2, time;
u32 rem;
local_irq_save(flags);
preempt_disable();
time1 = get_cycles();
for (i = 0; i < NR_LOOPS; i++) {
local_irq_restore(flags);
local_irq_save(flags);
}
time2 = get_cycles();
local_irq_restore(flags);
preempt_enable();
time = time2 - time1;
printk(KERN_ALERT "test results: time for disabling/enabling interrupts (STI/CLI)\n");
printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
printk(KERN_ALERT "total time: %llu\n", time);
time = div_u64_rem(time, NR_LOOPS, &rem);
printk(KERN_ALERT "-> enabling/disabling interrupts (STI/CLI) takes %llu cycles\n",
time);
printk(KERN_ALERT "test end\n");
}
s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
{
u64 quotient;
if (dividend < 0) {
quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder);
*remainder = -*remainder;
if (divisor > 0)
quotient = -quotient;
} else {
quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder);
if (divisor < 0)
quotient = -quotient;
}
return quotient;
}
/**
* __add_badblock_range() - Convert a physical address range to bad sectors
* @bb: badblocks instance to populate
* @ns_offset: namespace offset where the error range begins (in bytes)
* @len: number of bytes of poison to be added
*
* This assumes that the range provided with (ns_offset, len) is within
* the bounds of physical addresses for this namespace, i.e. lies in the
* interval [ns_start, ns_start + ns_size)
*/
static void __add_badblock_range(struct badblocks *bb, u64 ns_offset, u64 len)
{
const unsigned int sector_size = 512;
sector_t start_sector;
u64 num_sectors;
u32 rem;
start_sector = div_u64(ns_offset, sector_size);
num_sectors = div_u64_rem(len, sector_size, &rem);
if (rem)
num_sectors++;
if (unlikely(num_sectors > (u64)INT_MAX)) {
u64 remaining = num_sectors;
sector_t s = start_sector;
while (remaining) {
int done = min_t(u64, remaining, INT_MAX);
set_badblock(bb, s, done);
remaining -= done;
s += done;
}
} else
set_badblock(bb, start_sector, num_sectors);
}
/**
* stmmac_adjust_time
*
* @ptp: pointer to ptp_clock_info structure
* @delta: desired change in nanoseconds
*
* Description: this function will shift/adjust the hardware clock time.
*/
static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)
{
struct stmmac_priv *priv =
container_of(ptp, struct stmmac_priv, ptp_clock_ops);
unsigned long flags;
u32 sec, nsec;
u32 quotient, reminder;
int neg_adj = 0;
if (delta < 0) {
neg_adj = 1;
delta = -delta;
}
quotient = div_u64_rem(delta, 1000000000ULL, &reminder);
sec = quotient;
nsec = reminder;
spin_lock_irqsave(&priv->ptp_lock, flags);
priv->hw->ptp->adjust_systime(priv->ptpaddr, sec, nsec, neg_adj,
priv->plat->has_gmac4);
spin_unlock_irqrestore(&priv->ptp_lock, flags);
return 0;
}
/**
* ixgbe_ptp_setup_sdp
* @hw: the hardware private structure
*
* this function enables or disables the clock out feature on SDP0 for
* the X540 device. It will create a 1second periodic output that can
* be used as the PPS (via an interrupt).
*
* It calculates when the systime will be on an exact second, and then
* aligns the start of the PPS signal to that value. The shift is
* necessary because it can change based on the link speed.
*/
static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
{
struct ixgbe_hw *hw = &adapter->hw;
int shift = adapter->hw_cc.shift;
u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
u64 ns = 0, clock_edge = 0;
if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
(hw->mac.type == ixgbe_mac_X540)) {
/* disable the pin first */
IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
IXGBE_WRITE_FLUSH(hw);
esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
/*
* enable the SDP0 pin as output, and connected to the
* native function for Timesync (ClockOut)
*/
esdp |= (IXGBE_ESDP_SDP0_DIR |
IXGBE_ESDP_SDP0_NATIVE);
/*
* enable the Clock Out feature on SDP0, and allow
* interrupts to occur when the pin changes
*/
tsauxc = (IXGBE_TSAUXC_EN_CLK |
IXGBE_TSAUXC_SYNCLK |
IXGBE_TSAUXC_SDP0_INT);
/* clock period (or pulse length) */
clktiml = (u32)(NSECS_PER_SEC << shift);
clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
/*
* Account for the cyclecounter wrap-around value by
* using the converted ns value of the current time to
* check for when the next aligned second would occur.
*/
clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);
div_u64_rem(ns, NSECS_PER_SEC, &rem);
clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
/* specify the initial clock start time */
trgttiml = (u32)clock_edge;
trgttimh = (u32)(clock_edge >> 32);
IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
IXGBE_WRITE_FLUSH(hw);
} else {
static int DWC_ETH_QOS_get_time(struct ptp_clock_info *ptp,
struct timespec *ts)
{
struct DWC_ETH_QOS_prv_data *pdata =
container_of(ptp, struct DWC_ETH_QOS_prv_data, ptp_clock_ops);
struct hw_if_struct *hw_if = &(pdata->hw_if);
u64 ns;
u32 reminder;
unsigned long flags;
DBGPR_PTP("-->DWC_ETH_QOS_get_time\n");
spin_lock_irqsave(&pdata->ptp_lock, flags);
ns = hw_if->get_systime();
spin_unlock_irqrestore(&pdata->ptp_lock, flags);
ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &reminder);
ts->tv_nsec = reminder;
DBGPR_PTP("<--DWC_ETH_QOS_get_time: ts->tv_sec = %ld,"
"ts->tv_nsec = %ld\n", ts->tv_sec, ts->tv_nsec);
return 0;
}
static int DWC_ETH_QOS_adjust_time(struct ptp_clock_info *ptp, s64 delta)
{
struct DWC_ETH_QOS_prv_data *pdata =
container_of(ptp, struct DWC_ETH_QOS_prv_data, ptp_clock_ops);
struct hw_if_struct *hw_if = &(pdata->hw_if);
unsigned long flags;
u32 sec, nsec;
u32 quotient, reminder;
int neg_adj = 0;
DBGPR_PTP("-->DWC_ETH_QOS_adjust_time: delta = %lld\n", delta);
if (delta < 0) {
neg_adj = 1;
delta =-delta;
}
quotient = div_u64_rem(delta, 1000000000ULL, &reminder);
sec = quotient;
nsec = reminder;
spin_lock_irqsave(&pdata->ptp_lock, flags);
hw_if->adjust_systime(sec, nsec, neg_adj, pdata->one_nsec_accuracy);
spin_unlock_irqrestore(&pdata->ptp_lock, flags);
DBGPR_PTP("<--DWC_ETH_QOS_adjust_time\n");
return 0;
}
static int uptime_proc_show(struct seq_file *m, void *v)
{
struct timespec uptime;
struct timespec idle;
u64 idletime;
u64 nsec;
u32 rem;
int i;
idletime = 0;
for_each_possible_cpu(i)
idletime += (__force u64) kcpustat_cpu(i).cpustat[CPUTIME_IDLE];
do_posix_clock_monotonic_gettime(&uptime);
monotonic_to_bootbased(&uptime);
nsec = cputime64_to_jiffies64(idletime) * TICK_NSEC;
idle.tv_sec = div_u64_rem(nsec, NSEC_PER_SEC, &rem);
idle.tv_nsec = rem;
seq_printf(m, "%lu.%02lu %lu.%02lu\n",
(unsigned long) uptime.tv_sec,
(uptime.tv_nsec / (NSEC_PER_SEC / 100)),
(unsigned long) idle.tv_sec,
(idle.tv_nsec / (NSEC_PER_SEC / 100)));
return 0;
}
/**
* clear_update_marker - clear update marker.
* @ubi: UBI device description object
* @vol: volume description object
* @bytes: new data size in bytes
*
* This function clears the update marker for volume @vol, sets new volume
* data size and clears the "corrupted" flag (static volumes only). Returns
* zero in case of success and a negative error code in case of failure.
*/
static int clear_update_marker(struct ubi_device *ubi, struct ubi_volume *vol,
long long bytes)
{
int err;
struct ubi_vtbl_record vtbl_rec;
dbg_gen("clear update marker for volume %d", vol->vol_id);
vtbl_rec = ubi->vtbl[vol->vol_id];
ubi_assert(vol->upd_marker && vtbl_rec.upd_marker);
vtbl_rec.upd_marker = 0;
if (vol->vol_type == UBI_STATIC_VOLUME) {
vol->corrupted = 0;
vol->used_bytes = bytes;
vol->used_ebs = div_u64_rem(bytes, vol->usable_leb_size,
&vol->last_eb_bytes);
if (vol->last_eb_bytes)
vol->used_ebs += 1;
else
vol->last_eb_bytes = vol->usable_leb_size;
}
mutex_lock(&ubi->device_mutex);
err = ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec);
vol->upd_marker = 0;
mutex_unlock(&ubi->device_mutex);
return err;
}
/**
* @brief 64 bit divided by unsigned giving unsigned reminder.
*/
unsigned rem64u(u64 i, unsigned j)
{
u32 rem;
div_u64_rem(i, j, &rem);
return (unsigned)rem;
}
long long __divdi3(long long divided, long long divisor)
{
unsigned int reminder;
PR_DEBUG("divided is %lld", divided);
PR_DEBUG("divisor is %lld", divisor);
return div_u64_rem(divided, divisor, &reminder);
}
/*
* Erase an address range on the nor chip. The address range may extend
* one or more erase sectors. Return an error is there is a problem erasing.
*/
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
u32 addr, len;
uint32_t rem;
int ret;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
return -EINVAL;
addr = instr->addr;
len = instr->len;
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
if (ret)
return ret;
/* whole-chip erase? */
if (len == mtd->size) {
if (erase_chip(nor)) {
ret = -EIO;
goto erase_err;
}
/* REVISIT in some cases we could speed up erasing large regions
* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
* to use "small sector erase", but that's not always optimal.
*/
/* "sector"-at-a-time erase */
} else {
while (len) {
if (nor->erase(nor, addr)) {
ret = -EIO;
goto erase_err;
}
addr += mtd->erasesize;
len -= mtd->erasesize;
}
}
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
instr->state = MTD_ERASE_DONE;
mtd_erase_callback(instr);
return ret;
erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
instr->state = MTD_ERASE_FAILED;
return ret;
}
static ssize_t rmi_fn_34_data_write(struct file *filp,
struct kobject *kobj,
struct bin_attribute *attributes,
char *buf, loff_t pos, size_t count)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct rmi_function_device *fn = dev_get_drvdata(dev);
struct rmi_fn_34_data *fn34data = (struct rmi_fn_34_data *)fn->rfi->fndata;
unsigned int blocknum;
int error;
/* */
/* */
/* */
/* */
/*
*/
unsigned int remainder;
div_u64_rem(pos, fn34data->blocksize, &remainder);
if (remainder) {
printk(KERN_ERR "%s : Invalid byte offset of %llx leads to invalid block number.\n",
__func__, pos);
return -EINVAL;
}
/*
*/
blocknum = div_u64(pos, fn34data->blocksize);
/* */
error = rmi_write_multiple(fn->sensor, fn->function->functionDataBaseAddr,
(unsigned char *)&blocknum, 2);
if (error) {
printk(KERN_ERR "%s : Could not write block number to 0x%x\n",
__func__, fn->function->functionDataBaseAddr);
return error;
}
/* */
if (count) {
error = rmi_write_multiple(fn->sensor, fn->function->functionDataBaseAddr+2,
(unsigned char *)buf, count);
if (error) {
printk(KERN_ERR "%s : Could not write block data to 0x%x\n",
__func__, fn->function->functionDataBaseAddr+2);
return error;
}
}
return count;
}
/*******************************************************************
* mtd stuff
******************************************************************/
static int bcmmtd_erase(struct mtd_info *mtd, struct erase_info *instr)
{
uint32_t rem;
u32 addr,len;
int partition, offset;
int ret;
BlockCache *bc;
/* sanity czech */
if (instr->addr + instr->len > mtd->size)
return -EINVAL;
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
return -EINVAL;
addr = instr->addr;
len = instr->len;
#if DEBUG_VFLASH_MTD
printk("-->%s addr = %08x len = %08x\n", __func__, (unsigned int)addr, (unsigned int)len);
#endif
/* whole-chip erase is not supported */
if (len == mtd->size)
{
instr->state = MTD_ERASE_FAILED;
return -EIO;
}
else
{
while (len)
{
bc = find_block_cache(addr);
if (bc)
{
invalidate_block_cache(bc);
release_block_cache(bc);
}
partition = get_flash_partition(addr);
offset = addr - flash_partition_ptr[partition].offset;
ret = vflash_erase_block(partition, offset, mtd->erasesize);
if (ret < 0)
return ret;
addr += mtd->erasesize;
len -= mtd->erasesize;
}
}
instr->state = MTD_ERASE_DONE;
mtd_erase_callback(instr);
return 0;
}
static inline void
jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
{
/*
* Convert jiffies to nanoseconds and separate with
* one divide.
*/
u64 nsec = (u64)jiffies * TICK_NSEC;
u32 rem;
value->tv_sec = div_u64_rem(nsec, NSEC_PER_SEC, &rem);
value->tv_usec = rem / NSEC_PER_USEC;
}
char *
_i_compute(printval_u_t val, int base, char *s, int nrdigits)
{
int c;
div_u64_rem(val, base, (u32*)&c); // val % base ;
val = div_u64(val, base); // val /= base
if (val || nrdigits > 1)
s = _i_compute(val, base, s, nrdigits - 1);
*s++ = (c>9 ? c-10+'a' : c+'0');
return s;
}
static snd_pcm_uframes_t
dummy_hrtimer_pointer(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct dummy_hrtimer_pcm *dpcm = runtime->private_data;
u64 delta;
u32 pos;
delta = ktime_us_delta(hrtimer_cb_get_time(&dpcm->timer),
dpcm->base_time);
delta = div_u64(delta * runtime->rate + 999999, 1000000);
div_u64_rem(delta, runtime->buffer_size, &pos);
return pos;
}
static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
u64 ns;
u32 remainder;
unsigned long flags;
struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
struct pch_ts_regs *regs = pch_dev->regs;
spin_lock_irqsave(&pch_dev->register_lock, flags);
ns = pch_systime_read(regs);
spin_unlock_irqrestore(&pch_dev->register_lock, flags);
ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
ts->tv_nsec = remainder;
return 0;
}
/**
* e1000e_phc_gettime - Reads the current time from the hardware clock
* @ptp: ptp clock structure
* @ts: timespec structure to hold the current time value
*
* Read the timecounter and return the correct value in ns after converting
* it into a struct timespec.
**/
static int e1000e_phc_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
ptp_clock_info);
unsigned long flags;
u32 remainder;
u64 ns;
spin_lock_irqsave(&adapter->systim_lock, flags);
ns = timecounter_read(&adapter->tc);
spin_unlock_irqrestore(&adapter->systim_lock, flags);
ts->tv_sec = div_u64_rem(ns, NSEC_PER_SEC, &remainder);
ts->tv_nsec = remainder;
return 0;
}
/**
* ixgbe_ptp_gettime
* @ptp - the ptp clock structure
* @ts - timespec structure to hold the current time value
*
* read the timecounter and return the correct value on ns,
* after converting it into a struct timespec.
*/
static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
struct ixgbe_adapter *adapter =
container_of(ptp, struct ixgbe_adapter, ptp_caps);
u64 ns;
u32 remainder;
unsigned long flags;
spin_lock_irqsave(&adapter->tmreg_lock, flags);
ns = timecounter_read(&adapter->tc);
spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
ts->tv_nsec = remainder;
return 0;
}
