static void _update_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg) { u32 val; struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; if ((pll->flags & TEGRA_PLLM) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { val = pll_override_readl(params->pmc_divp_reg, pll); val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); val |= cfg->p << div_nmp->override_divp_shift; pll_override_writel(val, params->pmc_divp_reg, pll); val = pll_override_readl(params->pmc_divnm_reg, pll); val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | ~(divn_mask(pll) << div_nmp->override_divn_shift); val |= (cfg->m << div_nmp->override_divm_shift) | (cfg->n << div_nmp->override_divn_shift); pll_override_writel(val, params->pmc_divnm_reg, pll); } else { val = pll_readl_base(pll); val &= ~((divm_mask(pll) << div_nmp->divm_shift) | (divn_mask(pll) << div_nmp->divn_shift) | (divp_mask(pll) << div_nmp->divp_shift)); val |= ((cfg->m << div_nmp->divm_shift) | (cfg->n << div_nmp->divn_shift) | (cfg->p << div_nmp->divp_shift)); pll_writel_base(val, pll); } }
static void _get_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg) { u32 val; struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; if ((params->flags & TEGRA_PLLM) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { val = pll_override_readl(params->pmc_divp_reg, pll); cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); val = pll_override_readl(params->pmc_divnm_reg, pll); cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); } else {