int pch_gbe_probe(struct udevice *dev) { struct pch_gbe_priv *priv; struct eth_pdata *plat = dev_get_platdata(dev); void *iobase; /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes). This is guaranteed by * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER. */ priv = dev_get_priv(dev); priv->dev = dev; iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM); plat->iobase = (ulong)iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, plat->enetaddr); plat->phy_interface = PHY_INTERFACE_MODE_RGMII; pch_gbe_mdio_init(dev->name, priv->mac_regs); priv->bus = miiphy_get_dev_by_name(dev->name); return pch_gbe_phy_init(dev); }
/* * Configure the internal clock of both SIO HS-UARTs, if they are enabled * via FSP */ int arch_cpu_init_dm(void) { struct udevice *dev; void *base; int ret; int i; /* Loop over the 2 HS-UARTs */ for (i = 0; i < 2; i++) { ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev); if (!ret) { base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hsuart_clock_set(base); } } return 0; }
static int intel_i2c_probe(struct udevice *dev) { struct intel_i2c *priv = dev_get_priv(dev); u32 base; /* Save base address from PCI BAR */ priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, PCI_REGION_IO); base = priv->base; /* Set SMBus enable. */ dm_pci_write_config8(dev, HOSTC, HST_EN); /* Disable interrupts */ outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL); /* Set 32-byte data buffer mode */ outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL); return 0; }
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) { struct xhci_hccr *hccr; struct xhci_hcor *hcor; u32 cmd; hccr = (struct xhci_hccr *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hcor = (struct xhci_hcor *)((uintptr_t) hccr + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", (u32)hccr, (u32)hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); *ret_hccr = hccr; *ret_hcor = hcor; /* enable busmaster */ dm_pci_read_config32(dev, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_MASTER; dm_pci_write_config32(dev, PCI_COMMAND, cmd); }