/**
* @brief ADC DMA ISR service routine.
*
* @param[in] adcp pointer to the @p ADCDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* DMA errors handling.*/
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
/* DMA, this could help only if the DMA tries to access an unmapped
address space or violates alignment rules.*/
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
else {
/* It is possible that the conversion group has already be reset by the
ADC error handler, in this case this interrupt is spurious.*/
if (adcp->grpp != NULL) {
/* DMA buffer invalidation because data cache.*/
dmaBufferInvalidate(adcp->samples,
adcp->samples +
(adcp->depth * adcp->grpp->num_channels));
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(adcp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_adc_isr_half_code(adcp);
}
}
}
}
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
#if !DMA_BUFFERS_COHERENCE
/* DMA buffer invalidation because data cache, only invalidating the
half buffer just filled.
Only required if the ADC buffer is placed in a cache-able area.*/
dmaBufferInvalidate(buffer,
n * adcp->grpp->num_channels * sizeof (adcsample_t));
#else
(void)adcp;
#endif
/* Updating counters.*/
if (samples1 == buffer) {
nx += n;
}
else {
ny += n;
}
}
