void mew_bluetooth_transmit(uint8_t* data, uint16_t size, uint8_t sync_mode) {
mew_check_dma_memory((void*)data, "mew_bluetooth_transmit");
mew_wait_for_state(&_mew_dma_tx_state, 0);
_mew_dma_tx_state = 1;
dma_stream_reset(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_set_transfer_mode(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
dma_set_priority(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, DMA_SxCR_PL_HIGH);
dma_set_memory_size(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, DMA_SxCR_MSIZE_8BIT);
dma_set_peripheral_size(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, DMA_SxCR_PSIZE_8BIT);
dma_enable_memory_increment_mode(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_set_peripheral_address(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, (uint32_t) &MEW_BLUETOOTH_DMA_DR);
dma_channel_select(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, MEW_BLUETOOTH_DMA_CHANNEL_TX);
dma_set_memory_address(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, (uint32_t) data);
dma_set_number_of_data(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX, size);
dma_disable_fifo_error_interrupt(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_disable_half_transfer_interrupt(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_enable_transfer_complete_interrupt(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_enable_transfer_error_interrupt(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
dma_enable_transfer_complete_interrupt(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
__mew_bluetooth_clear_buf();
dma_enable_stream(MEW_BLUETOOTH_DMA, MEW_BLUETOOTH_DMA_STREAM_TX);
if (sync_mode == 1) {
mew_wait_for_state(&_mew_dma_tx_state, 0);
}
}
static void __spi_dma_setup(uint32_t stream, uint32_t maddr, size_t n)
{
while ((DMA1_SCR(stream) & DMA_SxCR_EN) != 0)
bl_dbg("Stream enabled");
/* Set peripheral address */
dma_set_peripheral_address(DMA1, stream, (uint32_t)&SPI2_DR);
/* Set memory address */
dma_set_memory_address(DMA1, stream, maddr);
/* Set total number of bytes to transfer */
dma_set_number_of_data(DMA1, stream, n);
/* Select channel, it is 0 for both RX and TX */
dma_channel_select(DMA1, stream, DMA_SxCR_CHSEL_0);
}
void usart_tx(char *buf, unsigned short len) {
usart_enable_tx_dma(USART1);
dma_stream_reset(DMA2, DMA_STREAM7);
dma_set_priority(DMA2, DMA_STREAM7, DMA_SxCR_PL_LOW);
dma_set_memory_size(DMA2, DMA_STREAM7, DMA_SxCR_MSIZE_8BIT);
dma_set_peripheral_size(DMA2, DMA_STREAM7, DMA_SxCR_PSIZE_8BIT);
dma_enable_memory_increment_mode(DMA2, DMA_STREAM7);
dma_set_transfer_mode(DMA2, DMA_STREAM7, DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
dma_set_peripheral_address(DMA2, DMA_STREAM7, (uint32_t) &USART1_DR);
dma_set_memory_address(DMA2, DMA_STREAM7, (uint32_t) buf);
dma_set_number_of_data(DMA2, DMA_STREAM7, len);
dma_enable_transfer_complete_interrupt(DMA2, DMA_STREAM7);
dma_channel_select(DMA2, DMA_STREAM7, DMA_SxCR_CHSEL_4);
dma_enable_stream(DMA2, DMA_STREAM7);
}
static void platform_init_adc() {
/* Set up DMA for the ADC */
nvic_enable_irq(NVIC_DMA2_STREAM0_IRQ);
nvic_set_priority(NVIC_DMA2_STREAM0_IRQ, 64);
/* Set up ADC */
for (int i = 0; i < NUM_SENSORS; ++i) {
if (config.sensors[i].method == SENSOR_ADC) {
adc_pins[i] = config.sensors[i].pin;
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, (1<<adc_pins[i]));
}
}
adc_off(ADC1);
adc_enable_scan_mode(ADC1);
adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_15CYC);
adc_power_on(ADC1);
adc_disable_dma(ADC1);
adc_enable_dma(ADC1);
adc_clear_overrun_flag(ADC1);
adc_set_dma_continue(ADC1);
dma_stream_reset(DMA2, DMA_STREAM0);
dma_set_priority(DMA2, DMA_STREAM0, DMA_SxCR_PL_HIGH);
dma_set_memory_size(DMA2, DMA_STREAM0, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA2, DMA_STREAM0, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA2, DMA_STREAM0);
dma_set_transfer_mode(DMA2, DMA_STREAM0, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_enable_circular_mode(DMA2, DMA_STREAM0);
dma_set_peripheral_address(DMA2, DMA_STREAM0, (uint32_t) &ADC1_DR);
dma_set_memory_address(DMA2, DMA_STREAM0, (uint32_t) adc_dma_buf);
dma_set_number_of_data(DMA2, DMA_STREAM0, NUM_SENSORS);
dma_enable_transfer_complete_interrupt(DMA2, DMA_STREAM0);
dma_channel_select(DMA2, DMA_STREAM0, DMA_SxCR_CHSEL_0);
dma_enable_stream(DMA2, DMA_STREAM0);
adc_set_regular_sequence(ADC1, NUM_SENSORS, adc_pins);
}
/*--------------------------------------------------------------------*/
void dma_setup(void)
{
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_DMA2EN);
/* ADC1 uses DMA controller 2 Stream 0 channel 0. */
/* Enable DMA2 clock and IRQ */
nvic_enable_irq(NVIC_DMA2_STREAM0_IRQ);
dma_stream_reset(DMA2,DMA_STREAM0);
dma_set_priority(DMA2,DMA_STREAM0,DMA_SxCR_PL_LOW);
dma_set_peripheral_size(DMA2,DMA_STREAM0,DMA_SxCR_PSIZE_32BIT);
/* The register to target is the ADC regular data register */
dma_set_peripheral_address(DMA2,DMA_STREAM0,(uint32_t) &ADC1_DR);
/* The array v[] is filled with the waveform data to be output */
dma_set_memory_size(DMA2,DMA_STREAM0,DMA_SxCR_MSIZE_32BIT);
dma_set_memory_address(DMA2,DMA_STREAM0,(uint32_t) v);
dma_set_number_of_data(DMA2,DMA_STREAM0,64);
dma_set_transfer_mode(DMA2,DMA_STREAM0, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_enable_memory_increment_mode(DMA2,DMA_STREAM0);
dma_enable_circular_mode(DMA2,DMA_STREAM0);
/* Don't use FIFO */
dma_enable_direct_mode(DMA2,DMA_STREAM0);
dma_enable_transfer_complete_interrupt(DMA2, DMA_STREAM0);
dma_channel_select(DMA2, DMA_STREAM0, DMA_SxCR_CHSEL_0);
dma_enable_stream(DMA2,DMA_STREAM0);
}
/*--------------------------------------------------------------------*/
static void dma_setup(void)
{
/* DAC channel 1 uses DMA controller 1 Stream 5 Channel 7. */
/* Enable DMA1 clock and IRQ */
rcc_periph_clock_enable(RCC_DMA1);
nvic_enable_irq(NVIC_DMA1_STREAM5_IRQ);
dma_stream_reset(DMA1, DMA_STREAM5);
dma_set_priority(DMA1, DMA_STREAM5, DMA_SxCR_PL_LOW);
dma_set_memory_size(DMA1, DMA_STREAM5, DMA_SxCR_MSIZE_8BIT);
dma_set_peripheral_size(DMA1, DMA_STREAM5, DMA_SxCR_PSIZE_8BIT);
dma_enable_memory_increment_mode(DMA1, DMA_STREAM5);
dma_enable_circular_mode(DMA1, DMA_STREAM5);
dma_set_transfer_mode(DMA1, DMA_STREAM5,
DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
/* The register to target is the DAC1 8-bit right justified data
register */
dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1);
/* The array v[] is filled with the waveform data to be output */
dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
dma_enable_transfer_complete_interrupt(DMA1, DMA_STREAM5);
dma_channel_select(DMA1, DMA_STREAM5, DMA_SxCR_CHSEL_7);
dma_enable_stream(DMA1, DMA_STREAM5);
}
void codecInit(void)
{
memset(adcBuffer, 0xaa, sizeof(adcBuffer));
// I2S2 alternate function mapping
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15);
gpio_set_af(GPIOB, GPIO_AF5, GPIO12 | GPIO13 | GPIO15);
gpio_set_af(GPIOB, GPIO_AF6, GPIO14); // I2S2ext_SD (I2S receive)
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_set_af(GPIOC, GPIO_AF5, GPIO6); // MCLK
gpio_set_output_options(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO12 | GPIO13 | GPIO15);
gpio_set_output_options(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO6);
// Set up SPI1
spi_reset(SPI1);
spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_MSBFIRST);
spi_set_nss_high(SPI1);
spi_enable_software_slave_management(SPI1);
spi_enable(SPI1);
// SPI1 alternate function mapping, set CSB signal high output
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7);
gpio_set(GPIOA, GPIO4);
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4);
codecConfig();
// Set up I2S for 48kHz 16-bit stereo.
// The input to the PLLI2S is 1MHz. Division factors are from
// table 126 in the data sheet.
//
// This gives us 1.536MHz SCLK = 16 bits * 2 channels * 48000 Hz
// and 12.288 MHz MCLK = 256 * 48000 Hz.
// With this PLL configuration the actual sampling frequency
// is nominally 47991 Hz.
spi_reset(SPI2);
RCC_PLLI2SCFGR = (3 << 28) | (258 << 6);
RCC_CR |= RCC_CR_PLLI2SON;
while (!(RCC_CR & RCC_CR_PLLI2SRDY));
const unsigned i2sdiv = 3;
SPI_I2SPR(SPI2) = SPI_I2SPR_MCKOE | SPI_I2SPR_ODD | i2sdiv;
SPI_I2SCFGR(SPI2) |= SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE |
(SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT << SPI_I2SCFGR_I2SCFG_LSB);
SPI_I2SCFGR(I2S2_EXT_BASE) = SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE |
(SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE << SPI_I2SCFGR_I2SCFG_LSB);
// Configure the DMA engine to stream data to the DAC.
dma_stream_reset(DMA1, DAC_DMA_STREAM);
dma_set_peripheral_address(DMA1, DAC_DMA_STREAM, (intptr_t)&SPI_DR(SPI2));
dma_set_memory_address(DMA1, DAC_DMA_STREAM, (intptr_t)dacBuffer[0]);
dma_set_memory_address_1(DMA1, DAC_DMA_STREAM, (intptr_t)dacBuffer[1]);
dma_set_number_of_data(DMA1, DAC_DMA_STREAM, BUFFER_SAMPLES);
dma_channel_select(DMA1, DAC_DMA_STREAM, DAC_DMA_CHANNEL);
dma_set_transfer_mode(DMA1, DAC_DMA_STREAM, DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
dma_set_memory_size(DMA1, DAC_DMA_STREAM, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA1, DAC_DMA_STREAM, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA1, DAC_DMA_STREAM);
dma_enable_double_buffer_mode(DMA1, DAC_DMA_STREAM);
dma_enable_stream(DMA1, DAC_DMA_STREAM);
// Configure the DMA engine to stream data from the ADC.
dma_stream_reset(DMA1, ADC_DMA_STREAM);
dma_set_peripheral_address(DMA1, ADC_DMA_STREAM, (intptr_t)&SPI_DR(I2S2_EXT_BASE));
dma_set_memory_address(DMA1, ADC_DMA_STREAM, (intptr_t)adcBuffer[0]);
dma_set_memory_address_1(DMA1, ADC_DMA_STREAM, (intptr_t)adcBuffer[1]);
dma_set_number_of_data(DMA1, ADC_DMA_STREAM, BUFFER_SAMPLES);
dma_channel_select(DMA1, ADC_DMA_STREAM, ADC_DMA_CHANNEL);
dma_set_transfer_mode(DMA1, ADC_DMA_STREAM, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_set_memory_size(DMA1, ADC_DMA_STREAM, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA1, ADC_DMA_STREAM, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA1, ADC_DMA_STREAM);
dma_enable_double_buffer_mode(DMA1, ADC_DMA_STREAM);
dma_enable_stream(DMA1, ADC_DMA_STREAM);
dma_enable_transfer_complete_interrupt(DMA1, ADC_DMA_STREAM);
nvic_enable_irq(NVIC_DMA1_STREAM3_IRQ);
nvic_set_priority(NVIC_DMA1_STREAM3_IRQ, 0x80); // 0 is most urgent
// Start transmitting data
spi_enable_rx_dma(I2S2_EXT_BASE);
spi_enable_tx_dma(SPI2);
}