int
main(int argc,
char **argv)
{
int simSize = 14;
int xx;
simResults = (double *) malloc(simSize*sizeof(double));
simCounts = (unsigned long *) malloc(simSize*sizeof(unsigned long));
simIndex = 0;
for(xx = 0; xx < simSize ; xx++)
{
simResults[xx] = 0.0;
simCounts[xx] = 0;
}
t_options Options;
t_arch Arch = { 0 };
enum e_operation Operation;
struct s_placer_opts PlacerOpts;
struct s_annealing_sched AnnealSched;
struct s_router_opts RouterOpts;
struct s_det_routing_arch RoutingArch;
t_segment_inf *Segments;
t_timing_inf Timing;
t_subblock_data Subblocks;
boolean ShowGraphics;
boolean TimingEnabled;
int GraphPause;
/* Print title message */
PrintTitle();
/* Print usage message if no args */
if(argc < 2)
{
PrintUsage();
exit(1);
}
/* Read in available inputs */
ReadOptions(argc, argv, &Options);
/* Determine whether timing is on or off */
TimingEnabled = IsTimingEnabled(Options);
/* Use inputs to configure VPR */
SetupVPR(Options, TimingEnabled, &Arch, &Operation, &PlacerOpts,
&AnnealSched, &RouterOpts, &RoutingArch, &Segments,
&Timing, &Subblocks, &ShowGraphics, &GraphPause);
/* Check inputs are reasonable */
CheckOptions(Options, TimingEnabled);
CheckArch(Arch, TimingEnabled);
/* Verify settings don't conflict or otherwise not make sense */
CheckSetup(Operation, PlacerOpts, AnnealSched, RouterOpts,
RoutingArch, Segments, Timing, Subblocks, Arch.Chans);
/* Output the current settings to console. */
ShowSetup(Options, Arch, TimingEnabled, Operation, PlacerOpts,
AnnealSched, RouterOpts, RoutingArch, Segments, Timing,
Subblocks);
if(Operation == TIMING_ANALYSIS_ONLY) {
do_constant_net_delay_timing_analysis(
Timing, Subblocks, Options.constant_net_delay);
return 0;
}
/* Startup X graphics */
set_graphics_state(ShowGraphics, GraphPause, RouterOpts.route_type);
if(ShowGraphics)
{
init_graphics("VPR: Versatile Place and Route for FPGAs");
alloc_draw_structs();
}
/* Do the actual operation */
place_and_route(Operation, PlacerOpts, Options.PlaceFile,
Options.NetFile, Options.ArchFile, Options.RouteFile,
AnnealSched, RouterOpts, RoutingArch,
Segments, Timing, &Subblocks, Arch.Chans);
/* Close down X Display */
if(ShowGraphics)
close_graphics();
/* free data structures */
free(Options.PlaceFile);
free(Options.NetFile);
free(Options.ArchFile);
free(Options.RouteFile);
freeArch(&Arch);
printf("\nTiming Results\n");
for(xx = 0; xx < simSize ; xx++)
{
if(simCounts[xx] != 0)
{
simResults[xx] /= (double) simCounts[xx];
}
printf("Index: %d\tAverage Clock: %f\n", xx, simResults[xx]);
}
free(simResults);
free(simCounts);
/* Return 0 to single success to scripts */
return 0;
}
/*
* Sets globals: nx, ny
* Allocs globals: chan_width_x, chan_width_y, grid
* Depends on num_clbs, pins_per_clb */
void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {
int *num_instances_type, *num_blocks_type;
int i;
int current, high, low;
boolean fit;
/* Read in netlist file for placement and routing */
if (vpr_setup.FileNameOpts.NetFile) {
read_netlist(vpr_setup.FileNameOpts.NetFile, &Arch, &num_blocks, &block,
&num_nets, &clb_net);
/* This is done so that all blocks have subblocks and can be treated the same */
check_netlist();
}
/* Output the current settings to console. */
printClusteredNetlistStats();
if (vpr_setup.Operation == TIMING_ANALYSIS_ONLY) {
do_constant_net_delay_timing_analysis(vpr_setup.Timing,
vpr_setup.constant_net_delay);
} else {
current = nint((float)sqrt((float)num_blocks)); /* current is the value of the smaller side of the FPGA */
low = 1;
high = -1;
num_instances_type = (int*) my_calloc(num_types, sizeof(int));
num_blocks_type = (int*) my_calloc(num_types, sizeof(int));
for (i = 0; i < num_blocks; i++) {
num_blocks_type[block[i].type->index]++;
}
if (Arch.clb_grid.IsAuto) {
/* Auto-size FPGA, perform a binary search */
while (high == -1 || low < high) {
/* Generate grid */
if (Arch.clb_grid.Aspect >= 1.0) {
ny = current;
nx = nint(current * Arch.clb_grid.Aspect);
} else {
nx = current;
ny = nint(current / Arch.clb_grid.Aspect);
}
#if DEBUG
vpr_printf(TIO_MESSAGE_INFO,
"Auto-sizing FPGA at x = %d y = %d\n", nx, ny);
#endif
alloc_and_load_grid(num_instances_type, &Arch);
freeGrid();
/* Test if netlist fits in grid */
fit = TRUE;
for (i = 0; i < num_types; i++) {
if (num_blocks_type[i] > num_instances_type[i]) {
fit = FALSE;
break;
}
}
/* get next value */
if (!fit) {
/* increase size of max */
if (high == -1) {
current = current * 2;
if (current > MAX_SHORT) {
vpr_printf(TIO_MESSAGE_ERROR,
"FPGA required is too large for current architecture settings.\n");
exit(1);
}
} else {
if (low == current)
current++;
low = current;
current = low + ((high - low) / 2);
}
} else {
high = current;
current = low + ((high - low) / 2);
}
}
/* Generate grid */
if (Arch.clb_grid.Aspect >= 1.0) {
ny = current;
nx = nint(current * Arch.clb_grid.Aspect);
} else {
nx = current;
ny = nint(current / Arch.clb_grid.Aspect);
}
alloc_and_load_grid(num_instances_type, &Arch);
vpr_printf(TIO_MESSAGE_INFO, "FPGA auto-sized to x = %d y = %d\n",
nx, ny);
} else {
nx = Arch.clb_grid.W;
ny = Arch.clb_grid.H;
alloc_and_load_grid(num_instances_type, &Arch);
}
vpr_printf(TIO_MESSAGE_INFO,
"The circuit will be mapped into a %d x %d array of clbs.\n",
nx, ny);
/* Test if netlist fits in grid */
fit = TRUE;
for (i = 0; i < num_types; i++) {
if (num_blocks_type[i] > num_instances_type[i]) {
fit = FALSE;
break;
}
}
if (!fit) {
vpr_printf(TIO_MESSAGE_ERROR,
"Not enough physical locations for type %s, number of blocks is %d but number of locations is %d.\n",
type_descriptors[i].name, num_blocks_type[i],
num_instances_type[i]);
exit(1);
}
vpr_printf(TIO_MESSAGE_INFO, "\n");
vpr_printf(TIO_MESSAGE_INFO, "Resource usage...\n");
for (i = 0; i < num_types; i++) {
vpr_printf(TIO_MESSAGE_INFO,
"\tNetlist %d\tblocks of type: %s\n",
num_blocks_type[i], type_descriptors[i].name);
vpr_printf(TIO_MESSAGE_INFO,
"\tArchitecture %d\tblocks of type: %s\n",
num_instances_type[i], type_descriptors[i].name);
}
vpr_printf(TIO_MESSAGE_INFO, "\n");
chan_width_x = (int *) my_malloc((ny + 1) * sizeof(int));
chan_width_y = (int *) my_malloc((nx + 1) * sizeof(int));
free(num_blocks_type);
free(num_instances_type);
}
}
int main (int argc, char *argv[]) {
#ifndef SPEC
char title[] = "\n\nVPR FPGA Placement and Routing Program Version 4.22 "
"by V. Betz.\n"
"Source completed Jan. 25, 1999; compiled " __DATE__ ".\n"
"This code is licensed only for non-commercial use.\n\n";
#else
char title[] = "\n\nVPR FPGA Placement and Routing Program Version 4.00-spec"
"\nSource completed Sept. 19, 1997.\n\n";
#endif
char net_file[BUFSIZE], place_file[BUFSIZE], arch_file[BUFSIZE];
char route_file[BUFSIZE];
float aspect_ratio;
boolean full_stats, user_sized;
char pad_loc_file[BUFSIZE];
enum e_operation operation;
boolean verify_binary_search;
boolean show_graphics;
int gr_automode;
struct s_annealing_sched annealing_sched;
struct s_placer_opts placer_opts;
struct s_router_opts router_opts;
struct s_det_routing_arch det_routing_arch;
t_segment_inf *segment_inf;
t_timing_inf timing_inf;
t_subblock_data subblock_data;
t_chan_width_dist chan_width_dist;
float constant_net_delay;
printf("%s",title);
placer_opts.pad_loc_file = pad_loc_file;
/* Parse the command line. */
parse_command (argc, argv, net_file, arch_file, place_file, route_file,
&operation, &aspect_ratio, &full_stats, &user_sized, &verify_binary_search,
&gr_automode, &show_graphics, &annealing_sched, &placer_opts, &router_opts,
&timing_inf.timing_analysis_enabled, &constant_net_delay);
/* Parse input circuit and architecture */
get_input (net_file, arch_file, placer_opts.place_cost_type,
placer_opts.num_regions, aspect_ratio, user_sized,
router_opts.route_type, &det_routing_arch, &segment_inf,
&timing_inf, &subblock_data, &chan_width_dist);
if (full_stats == TRUE)
print_lambda ();
#ifdef DEBUG
print_netlist ("net.echo", net_file, subblock_data);
print_arch (arch_file, router_opts.route_type, det_routing_arch,
segment_inf, timing_inf, subblock_data, chan_width_dist);
#endif
if (operation == TIMING_ANALYSIS_ONLY) { /* Just run the timing analyzer. */
do_constant_net_delay_timing_analysis (timing_inf, subblock_data,
constant_net_delay);
free_subblock_data (&subblock_data);
exit (0);
}
set_graphics_state (show_graphics, gr_automode, router_opts.route_type);
if (show_graphics) {
/* Get graphics going */
init_graphics("VPR: Versatile Place and Route for FPGAs");
alloc_draw_structs ();
}
fflush (stdout);
place_and_route (operation, placer_opts, place_file, net_file, arch_file,
route_file, full_stats, verify_binary_search, annealing_sched, router_opts,
det_routing_arch, segment_inf, timing_inf, &subblock_data,
chan_width_dist);
if (show_graphics)
close_graphics(); /* Close down X Display */
exit (0);
}
