static void
smp_chrp_setup_cpu(int cpu_nr)
{
static atomic_t ready = ATOMIC_INIT(1);
static volatile int frozen = 0;
if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
/* timebases already synced under the hypervisor. */
paca[cpu_nr].next_jiffy_update_tb = tb_last_stamp = get_tb();
if (cpu_nr == 0) {
systemcfg->tb_orig_stamp = tb_last_stamp;
/* Should update naca->stamp_xsec.
* For now we leave it which means the time can be some
* number of msecs off until someone does a settimeofday()
*/
}
smp_tb_synchronized = 1;
} else {
if (cpu_nr == 0) {
/* wait for all the others */
while (atomic_read(&ready) < smp_num_cpus)
barrier();
atomic_set(&ready, 1);
/* freeze the timebase */
rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
mb();
frozen = 1;
set_tb(0, 0);
paca[0].next_jiffy_update_tb = 0;
smp_space_timers(smp_num_cpus);
while (atomic_read(&ready) < smp_num_cpus)
barrier();
/* thaw the timebase again */
rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
mb();
frozen = 0;
tb_last_stamp = get_tb();
systemcfg->tb_orig_stamp = tb_last_stamp;
smp_tb_synchronized = 1;
} else {
atomic_inc(&ready);
while (!frozen)
barrier();
set_tb(0, 0);
mb();
atomic_inc(&ready);
while (frozen)
barrier();
}
}
if (OpenPIC_Addr) {
do_openpic_setup_cpu();
} else {
if (cpu_nr > 0)
xics_setup_cpu();
}
}
static void __init smp_core99_setup_cpu(int cpu_nr)
{
/* Setup openpic */
do_openpic_setup_cpu();
if (cpu_nr == 0) {
extern void g5_phy_disable_cpu1(void);
/* If we didn't start the second CPU, we must take
* it off the bus
*/
if (num_online_cpus() < 2)
g5_phy_disable_cpu1();
if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
}
}
static void __init
smp_chrp_setup_cpu(int cpu_nr)
{
static atomic_t ready = ATOMIC_INIT(1);
static volatile int frozen = 0;
if (cpu_nr == 0) {
/* wait for all the others */
while (atomic_read(&ready) < smp_num_cpus)
barrier();
atomic_set(&ready, 1);
/* freeze the timebase */
call_rtas("freeze-time-base", 0, 1, NULL);
mb();
frozen = 1;
/* XXX assumes this is not a 601 */
set_tb(0, 0);
last_jiffy_stamp(0) = 0;
while (atomic_read(&ready) < smp_num_cpus)
barrier();
/* thaw the timebase again */
call_rtas("thaw-time-base", 0, 1, NULL);
mb();
frozen = 0;
smp_tb_synchronized = 1;
} else {
atomic_inc(&ready);
while (!frozen)
barrier();
set_tb(0, 0);
last_jiffy_stamp(0) = 0;
mb();
atomic_inc(&ready);
while (frozen)
barrier();
}
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static void __init
smp_pplus_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static void __devinit
smp_chrp_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}