int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock) { int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock); int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock); if ((lanes == 0) || (dp_clock == 0)) return MODE_CLOCK_HIGH; return MODE_OK; }
void radeon_dp_set_link_config(struct drm_connector *connector, struct drm_display_mode *mode) { struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) && (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) return; radeon_connector = to_radeon_connector(connector); if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; dig_connector->dp_clock = dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock); dig_connector->dp_lane_count = dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock); }