void intel_batchbuffer_finish(struct intel_batchbuffer *batch) { struct _DriFenceObject *fence = intel_batchbuffer_flush(batch); driFenceReference(fence); driFenceFinish(fence, 3, GL_FALSE); driFenceUnReference(fence); }
static void intel_display_surface(struct egl_drm_drawable *draw, struct pipe_surface *surf) { struct intel_context *intel = NULL; struct intel_framebuffer *intel_fb = (struct intel_framebuffer *)draw->priv; struct _DriFenceObject *fence; //const int srcWidth = surf->width; //const int srcHeight = surf->height; intel = intel_fb->device->dummy; if (!intel) { printf("No dummy context\n"); return; } const int dstWidth = intel_fb->front->width; const int dstHeight = intel_fb->front->height; const int dstPitch = intel_fb->front->pitch / 4;//draw->front.cpp; const int cpp = 4;//intel_fb->front->cpp; const int srcPitch = surf->stride / cpp; int BR13, CMD; //int i; BR13 = (dstPitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); BEGIN_BATCH(8, 2); OUT_BATCH(CMD); OUT_BATCH(BR13); OUT_BATCH((0 << 16) | 0); OUT_BATCH((dstHeight << 16) | dstWidth); OUT_RELOC(intel_fb->front_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0); OUT_BATCH((0 << 16) | 0); OUT_BATCH((srcPitch * cpp) & 0xffff); OUT_RELOC(dri_bo(surf->buffer), DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0); fence = intel_be_batchbuffer_flush(intel->base.batch); driFenceUnReference(&fence); intel_be_batchbuffer_finish(intel->base.batch); }
void intel_batchbuffer_free(struct intel_batchbuffer *batch) { if (batch->last_fence) { driFenceFinish(batch->last_fence, DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW, GL_FALSE); driFenceUnReference(batch->last_fence); batch->last_fence = NULL; } if (batch->map) { driBOUnmap(batch->buffer); batch->map = NULL; } driBOUnReference(batch->buffer); batch->buffer = NULL; free(batch); }
/** * Display a colorbuffer surface in an X window. * Used for SwapBuffers and flushing front buffer rendering. * * \param dPriv the window/drawable to display into * \param surf the surface to display * \param rect optional subrect of surface to display (may be NULL). */ void intelDisplaySurface(__DRIdrawablePrivate *dPriv, struct pipe_surface *surf, const drm_clip_rect_t *rect) { struct intel_screen *intelScreen = intel_screen(dPriv->driScreenPriv); struct intel_context *intel = intelScreen->dummyContext; DBG(SWAP, "%s\n", __FUNCTION__); if (!intel) { /* XXX this is where some kind of extra/meta context could be useful */ return; } if (intel->last_swap_fence) { driFenceFinish(intel->last_swap_fence, DRM_FENCE_TYPE_EXE, TRUE); driFenceUnReference(&intel->last_swap_fence); intel->last_swap_fence = NULL; } intel->last_swap_fence = intel->first_swap_fence; intel->first_swap_fence = NULL; /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets * should work regardless. */ LOCK_HARDWARE(intel); /* if this drawable isn't currently bound the LOCK_HARDWARE done on the * current context (which is what intelScreenContext should return) might * not get a contended lock and thus cliprects not updated (tests/manywin) */ if (intel_context(dPriv->driContextPriv) != intel) DRI_VALIDATE_DRAWABLE_INFO(intel->driScreen, dPriv); if (dPriv && dPriv->numClipRects) { const int srcWidth = surf->width; const int srcHeight = surf->height; const int nbox = dPriv->numClipRects; const drm_clip_rect_t *pbox = dPriv->pClipRects; const int pitch = intelScreen->front.pitch / intelScreen->front.cpp; const int cpp = intelScreen->front.cpp; const int srcpitch = surf->stride / cpp; int BR13, CMD; int i; ASSERT(surf->buffer); ASSERT(surf->cpp == cpp); DBG(SWAP, "screen pitch %d src surface pitch %d\n", pitch, surf->stride); if (cpp == 2) { BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24); CMD = XY_SRC_COPY_BLT_CMD; } else { BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); } for (i = 0; i < nbox; i++, pbox++) { drm_clip_rect_t box; drm_clip_rect_t sbox; if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || pbox->x2 > intelScreen->front.width || pbox->y2 > intelScreen->front.height) { /* invalid cliprect, skip it */ continue; } box = *pbox; if (rect) { /* intersect cliprect with user-provided src rect */ drm_clip_rect_t rrect; rrect.x1 = dPriv->x + rect->x1; rrect.y1 = (dPriv->h - rect->y1 - rect->y2) + dPriv->y; rrect.x2 = rect->x2 + rrect.x1; rrect.y2 = rect->y2 + rrect.y1; if (rrect.x1 > box.x1) box.x1 = rrect.x1; if (rrect.y1 > box.y1) box.y1 = rrect.y1; if (rrect.x2 < box.x2) box.x2 = rrect.x2; if (rrect.y2 < box.y2) box.y2 = rrect.y2; if (box.x1 > box.x2 || box.y1 > box.y2) continue; } /* restrict blit to size of actually rendered area */ if (box.x2 - box.x1 > srcWidth) box.x2 = srcWidth + box.x1; if (box.y2 - box.y1 > srcHeight) box.y2 = srcHeight + box.y1; DBG(SWAP, "box x1 x2 y1 y2 %d %d %d %d\n", box.x1, box.x2, box.y1, box.y2); sbox.x1 = box.x1 - dPriv->x; sbox.y1 = box.y1 - dPriv->y; assert(box.x1 < box.x2); assert(box.y1 < box.y2); /* XXX this could be done with pipe->surface_copy() */ /* XXX should have its own batch buffer */ if (!BEGIN_BATCH(8, 2)) { /* * Since we share this batch buffer with a context * we can't flush it since that risks a GPU lockup */ assert(0); continue; } OUT_BATCH(CMD); OUT_BATCH(BR13); OUT_BATCH((box.y1 << 16) | box.x1); OUT_BATCH((box.y2 << 16) | box.x2); OUT_RELOC(intelScreen->front.buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0); OUT_BATCH((sbox.y1 << 16) | sbox.x1); OUT_BATCH((srcpitch * cpp) & 0xffff); OUT_RELOC(dri_bo(surf->buffer), DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0); } if (intel->first_swap_fence) driFenceUnReference(&intel->first_swap_fence); intel->first_swap_fence = intel_be_batchbuffer_flush(intel->base.batch); } UNLOCK_HARDWARE(intel); if (intel->lastStamp != dPriv->lastStamp) { intelUpdateWindowSize(dPriv); intel->lastStamp = dPriv->lastStamp; } }
/* TODO: Push this whole function into bufmgr. */ static void do_flush_locked(struct intel_batchbuffer *batch, GLuint used, GLboolean ignore_cliprects, GLboolean allow_unlock) { GLuint *ptr; GLuint i; struct intel_context *intel = batch->intel; unsigned fenceFlags; struct _DriFenceObject *fo; driBOValidateList(batch->intel->driFd, &batch->list); /* Apply the relocations. This nasty map indicates to me that the * whole task should be done internally by the memory manager, and * that dma buffers probably need to be pinned within agp space. */ ptr = (GLuint *) driBOMap(batch->buffer, DRM_BO_FLAG_WRITE, DRM_BO_HINT_ALLOW_UNFENCED_MAP); for (i = 0; i < batch->nr_relocs; i++) { struct buffer_reloc *r = &batch->reloc[i]; ptr[r->offset / 4] = driBOOffset(r->buf) + r->delta; } if (INTEL_DEBUG & DEBUG_BATCH) intel_dump_batchbuffer(0, ptr, used); driBOUnmap(batch->buffer); batch->map = NULL; /* Throw away non-effective packets. Won't work once we have * hardware contexts which would preserve statechanges beyond a * single buffer. */ if (!(intel->numClipRects == 0 && !ignore_cliprects)) { intel_batch_ioctl(batch->intel, driBOOffset(batch->buffer), used, ignore_cliprects, allow_unlock); } /* * Kernel fencing. The flags tells the kernel that we've * programmed an MI_FLUSH. */ fenceFlags = DRM_I915_FENCE_FLAG_FLUSHED; fo = driFenceBuffers(batch->intel->driFd, "Batch fence", fenceFlags); /* * User space fencing. */ driBOFence(batch->buffer, fo); if (driFenceType(fo) == DRM_FENCE_TYPE_EXE) { /* * Oops. We only validated a batch buffer. This means we * didn't do any proper rendering. Discard this fence object. */ driFenceUnReference(fo); } else { driFenceUnReference(batch->last_fence); batch->last_fence = fo; for (i = 0; i < batch->nr_relocs; i++) { struct buffer_reloc *r = &batch->reloc[i]; driBOFence(r->buf, fo); } } if (intel->numClipRects == 0 && !ignore_cliprects) { if (allow_unlock) { UNLOCK_HARDWARE(intel); sched_yield(); LOCK_HARDWARE(intel); } intel->vtbl.lost_hardware(intel); } }
/* Pros: * - no waiting for idle before updating framebuffer. * * Cons: * - if upload is by memcpy, this may actually be slower than fallback path. * - uploads the whole image even if destination is clipped * * Need to benchmark. * * Given the questions about performance, implement for pbo's only. * This path is definitely a win if the pbo is already in agp. If it * turns out otherwise, we can add the code necessary to upload client * data to agp space before performing the blit. (Though it may turn * out to be better/simpler just to use the texture engine). */ static GLboolean do_blit_drawpixels(GLcontext * ctx, GLint x, GLint y, GLsizei width, GLsizei height, GLenum format, GLenum type, const struct gl_pixelstore_attrib *unpack, const GLvoid * pixels) { struct intel_context *intel = intel_context(ctx); struct intel_region *dest = intel_drawbuf_region(intel); struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj); GLuint src_offset; GLuint rowLength; struct _DriFenceObject *fence = NULL; if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s\n", __FUNCTION__); if (!dest) { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - no dest\n", __FUNCTION__); return GL_FALSE; } if (src) { /* This validation should be done by core mesa: */ if (!_mesa_validate_pbo_access(2, unpack, width, height, 1, format, type, pixels)) { _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawPixels"); return GL_TRUE; } } else { /* PBO only for now: */ if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - not PBO\n", __FUNCTION__); return GL_FALSE; } if (!intel_check_blit_format(dest, format, type)) { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - bad format for blit\n", __FUNCTION__); return GL_FALSE; } if (!intel_check_blit_fragment_ops(ctx)) { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - bad GL fragment state for blitter\n", __FUNCTION__); return GL_FALSE; } if (ctx->Pixel.ZoomX != 1.0F) { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - bad PixelZoomX for blit\n", __FUNCTION__); return GL_FALSE; } if (unpack->RowLength > 0) rowLength = unpack->RowLength; else rowLength = width; if (ctx->Pixel.ZoomY == -1.0F) { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - bad PixelZoomY for blit\n", __FUNCTION__); return GL_FALSE; /* later */ y -= height; } else if (ctx->Pixel.ZoomY == 1.0F) { rowLength = -rowLength; } else { if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - bad PixelZoomY for blit\n", __FUNCTION__); return GL_FALSE; } src_offset = (GLuint) _mesa_image_address(2, unpack, pixels, width, height, format, type, 0, 0, 0); intelFlush(&intel->ctx); LOCK_HARDWARE(intel); if (intel->driDrawable->numClipRects) { __DRIdrawablePrivate *dPriv = intel->driDrawable; int nbox = dPriv->numClipRects; drm_clip_rect_t *box = dPriv->pClipRects; drm_clip_rect_t rect; drm_clip_rect_t dest_rect; struct _DriBufferObject *src_buffer = intel_bufferobj_buffer(intel, src, INTEL_READ); int i; dest_rect.x1 = dPriv->x + x; dest_rect.y1 = dPriv->y + dPriv->h - (y + height); dest_rect.x2 = dest_rect.x1 + width; dest_rect.y2 = dest_rect.y1 + height; for (i = 0; i < nbox; i++) { if (!intel_intersect_cliprects(&rect, &dest_rect, &box[i])) continue; intelEmitCopyBlit(intel, dest->cpp, rowLength, src_buffer, src_offset, dest->pitch, dest->buffer, 0, rect.x1 - dest_rect.x1, rect.y2 - dest_rect.y2, rect.x1, rect.y1, rect.x2 - rect.x1, rect.y2 - rect.y1, ctx->Color.ColorLogicOpEnabled ? ctx->Color.LogicOp : GL_COPY); } fence = intel_batchbuffer_flush(intel->batch); driFenceReference(fence); } UNLOCK_HARDWARE(intel); if (fence) { driFenceFinish(fence, DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW, GL_FALSE); driFenceUnReference(fence); } if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - DONE\n", __FUNCTION__); return GL_TRUE; }