Exemple #1
0
int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	struct drm_agp_mode mode;

	mode = *(struct drm_agp_mode *) data;

	return drm_agp_enable(dev, mode);
}
Exemple #2
0
int drm_agp_enable_ioctl(DRM_IOCTL_ARGS)
{
	drm_agp_mode_t mode;
	DRM_DEVICE;

	mode = *(drm_agp_mode_t *) data;

	return drm_agp_enable(dev, mode);
}
Exemple #3
0
int drm_agp_enable_ioctl(struct inode *inode, struct file *filp,
			 unsigned int cmd, unsigned long arg)
{
	drm_file_t *priv = filp->private_data;
	drm_device_t *dev = priv->head->dev;
	drm_agp_mode_t mode;

	if (copy_from_user(&mode, (drm_agp_mode_t __user *) arg, sizeof(mode)))
		return -EFAULT;

	return drm_agp_enable(dev, mode);
}
Exemple #4
0
void
nouveau_agp_reset(struct nouveau_drm *drm)
{
#if __OS_HAS_AGP
	struct nouveau_device *device = nv_device(drm->device);
	struct drm_device *dev = drm->dev;
	u32 save[2];
	int ret;

	if (!nouveau_agp_enabled(drm))
		return;

	/* First of all, disable fast writes, otherwise if it's
	 * already enabled in the AGP bridge and we disable the card's
	 * AGP controller we might be locking ourselves out of it. */
	if ((nv_rd32(device, NV04_PBUS_PCI_NV_19) |
	     dev->agp->mode) & PCI_AGP_COMMAND_FW) {
		struct drm_agp_info info;
		struct drm_agp_mode mode;

		ret = drm_agp_info(dev, &info);
		if (ret)
			return;

		mode.mode  = get_agp_mode(drm, &info);
		mode.mode &= ~PCI_AGP_COMMAND_FW;

		ret = drm_agp_enable(dev, mode);
		if (ret)
			return;
	}


	/* clear busmaster bit, and disable AGP */
	save[0] = nv_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
	nv_wr32(device, NV04_PBUS_PCI_NV_19, 0);

	/* reset PGRAPH, PFIFO and PTIMER */
	save[1] = nv_mask(device, 0x000200, 0x00011100, 0x00000000);
	nv_mask(device, 0x000200, 0x00011100, save[1]);

	/* and restore bustmaster bit (gives effect of resetting AGP) */
	nv_wr32(device, NV04_PBUS_PCI_NV_1, save[0]);
#endif
}
Exemple #5
0
void
nouveau_agp_init(struct nouveau_drm *drm)
{
#if __OS_HAS_AGP
	struct nouveau_device *device = nv_device(drm->device);
	struct drm_device *dev = drm->dev;
	struct drm_agp_info info;
	struct drm_agp_mode mode;
	int ret;

	if (!nouveau_agp_enabled(drm))
		return;
	drm->agp.stat = DISABLE;

	ret = drm_agp_acquire(dev);
	if (ret) {
		nv_error(device, "unable to acquire AGP: %d\n", ret);
		return;
	}

	ret = drm_agp_info(dev, &info);
	if (ret) {
		nv_error(device, "unable to get AGP info: %d\n", ret);
		return;
	}

	/* see agp.h for the AGPSTAT_* modes available */
	mode.mode = get_agp_mode(drm, &info);

	ret = drm_agp_enable(dev, mode);
	if (ret) {
		nv_error(device, "unable to enable AGP: %d\n", ret);
		return;
	}

	drm->agp.stat = ENABLED;
	drm->agp.base = info.aperture_base;
	drm->agp.size = info.aperture_size;
#endif
}
Exemple #6
0
int radeon_agp_init(struct radeon_device *rdev)
{
#if __OS_HAS_AGP
    struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
    struct drm_agp_mode mode;
    struct drm_agp_info info;
    uint32_t agp_status;
    int default_mode;
    bool is_v3;
    int ret;

    /* Acquire AGP. */
    if (!rdev->ddev->agp->acquired) {
        ret = drm_agp_acquire(rdev->ddev);
        if (ret) {
            DRM_ERROR("Unable to acquire AGP: %d\n", ret);
            return ret;
        }
    }

    ret = drm_agp_info(rdev->ddev, &info);
    if (ret) {
        drm_agp_release(rdev->ddev);
        DRM_ERROR("Unable to get AGP info: %d\n", ret);
        return ret;
    }

    if (rdev->ddev->agp->agp_info.aper_size < 32) {
        drm_agp_release(rdev->ddev);
        dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
                 "need at least 32M, disabling AGP\n",
                 rdev->ddev->agp->agp_info.aper_size);
        return -EINVAL;
    }

    mode.mode = info.mode;
    agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
    is_v3 = !!(agp_status & RADEON_AGPv3_MODE);

    if (is_v3) {
        default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
    } else {
        if (agp_status & RADEON_AGP_4X_MODE) {
            default_mode = 4;
        } else if (agp_status & RADEON_AGP_2X_MODE) {
            default_mode = 2;
        } else {
            default_mode = 1;
        }
    }

    /* Apply AGPMode Quirks */
    while (p && p->chip_device != 0) {
        if (info.id_vendor == p->hostbridge_vendor &&
                info.id_device == p->hostbridge_device &&
                rdev->pdev->vendor == p->chip_vendor &&
                rdev->pdev->device == p->chip_device &&
                rdev->pdev->subsystem_vendor == p->subsys_vendor &&
                rdev->pdev->subsystem_device == p->subsys_device) {
            default_mode = p->default_mode;
        }
        ++p;
    }

    if (radeon_agpmode > 0) {
        if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
                (radeon_agpmode > (is_v3 ? 8 : 4)) ||
                (radeon_agpmode & (radeon_agpmode - 1))) {
            DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
                      radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
                      default_mode);
            radeon_agpmode = default_mode;
        } else {
            DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
        }
    } else {
        radeon_agpmode = default_mode;
    }

    mode.mode &= ~RADEON_AGP_MODE_MASK;
    if (is_v3) {
        switch (radeon_agpmode) {
        case 8:
            mode.mode |= RADEON_AGPv3_8X_MODE;
            break;
        case 4:
        default:
            mode.mode |= RADEON_AGPv3_4X_MODE;
            break;
        }
    } else {
        switch (radeon_agpmode) {
        case 4:
            mode.mode |= RADEON_AGP_4X_MODE;
            break;
        case 2:
            mode.mode |= RADEON_AGP_2X_MODE;
            break;
        case 1:
        default:
            mode.mode |= RADEON_AGP_1X_MODE;
            break;
        }
    }

    mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
    ret = drm_agp_enable(rdev->ddev, mode);
    if (ret) {
        DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
        drm_agp_release(rdev->ddev);
        return ret;
    }

    rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
    rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;

    /* workaround some hw issues */
    if (rdev->family < CHIP_R200) {
        WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
    }
    return 0;
#else
    return 0;
#endif
}