void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag)
{
if (flag & RCB_INT_FLAG_TX)
dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);
if (flag & RCB_INT_FLAG_RX)
dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);
}
/* clr exc irq for xge*/
static void hns_xgmac_exc_irq_en(struct mac_driver *drv, u32 en)
{
u32 clr_vlue = 0xfffffffful;
u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
dsaf_write_dev(drv, XGMAC_INT_STATUS_REG, clr_vlue);
dsaf_write_dev(drv, XGMAC_INT_ENABLE_REG, msk_vlue);
}
void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
{
u32 int_mask_en = !!mask;
if (flag & RCB_INT_FLAG_TX)
dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
if (flag & RCB_INT_FLAG_RX)
dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
}
static void hns_xgmac_set_pausefrm_mac_addr(void *mac_drv, char *mac_addr)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
| (mac_addr[3] << 16) | (mac_addr[2] << 24);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG, low_val);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG, high_val);
}
void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
{
if (flag & RCB_INT_FLAG_TX) {
dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);
}
if (flag & RCB_INT_FLAG_RX) {
dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);
dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);
}
}
void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
{
int i;
int reg_value;
for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
reg_value = dsaf_read_dev(ppe_cb,
PPEV2_INDRECTION_TBL_REG + i * 0x4);
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
PPEV2_CFG_RSS_TBL_4N0_S,
rss_tab[i * 4 + 0] & 0x1F);
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
PPEV2_CFG_RSS_TBL_4N1_S,
rss_tab[i * 4 + 1] & 0x1F);
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
PPEV2_CFG_RSS_TBL_4N2_S,
rss_tab[i * 4 + 2] & 0x1F);
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
PPEV2_CFG_RSS_TBL_4N3_S,
rss_tab[i * 4 + 3] & 0x1F);
dsaf_write_dev(
ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
}
}
/* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester
*@q: hnae_queue
*@buf_size: buffer size set to hw
*/
void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size)
{
u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
bd_size_type);
}
static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
| (mac_addr[3] << 16) | (mac_addr[2] << 24);
u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B);
dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
high_val | (sta_addr_en << GMAC_ADDR_EN_B));
}
/*clr ppe exception irq*/
static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
{
u32 clr_vlue = 0xfffffffful;
u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
u32 vld_msk = 0;
/*only care bit 0,1,7*/
dsaf_set_bit(vld_msk, 0, 1);
dsaf_set_bit(vld_msk, 1, 1);
dsaf_set_bit(vld_msk, 7, 1);
/*clr sts**/
dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
/*for some reserved bits, so set 0**/
dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
}
/**
*hns_xgmac_pma_fec_enable - xgmac PMA FEC enable
*@drv: mac driver
*@tx_value: tx value
*@rx_value: rx value
*return status
*/
static void hns_xgmac_pma_fec_enable(struct mac_driver *drv, u32 tx_value,
u32 rx_value)
{
u32 origin = dsaf_read_dev(drv, XGMAC_PMA_FEC_CONTROL_REG);
dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_TX_B, !!tx_value);
dsaf_set_bit(origin, XGMAC_PMA_FEC_CTL_RX_B, !!rx_value);
dsaf_write_dev(drv, XGMAC_PMA_FEC_CONTROL_REG, origin);
}
void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
{
u32 key_item;
for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
rss_key[key_item]);
}
/**
*hns_xgmac_pausefrm_cfg - set pause param about xgmac
*@mac_drv: mac driver
*@newval:enable of pad and crc
*/
static void hns_xgmac_pausefrm_cfg(void *mac_drv, u32 rx_en, u32 tx_en)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 origin = dsaf_read_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG);
dsaf_set_bit(origin, XGMAC_PAUSE_CTL_TX_B, !!tx_en);
dsaf_set_bit(origin, XGMAC_PAUSE_CTL_RX_B, !!rx_en);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG, origin);
}
static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
{
u32 tx_loop_pkt_pri;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
}
/**
*hns_rcb_reset_ring_hw - ring reset
*@q: ring struct pointer
*/
void hns_rcb_reset_ring_hw(struct hnae_queue *q)
{
u32 wait_cnt;
u32 try_cnt = 0;
u32 could_ret;
u32 tx_fbd_num;
while (try_cnt++ < RCB_RESET_TRY_TIMES) {
usleep_range(100, 200);
tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
if (tx_fbd_num)
continue;
dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
msleep(20);
could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
wait_cnt = 0;
while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
msleep(20);
could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
wait_cnt++;
}
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
if (could_ret)
break;
}
if (try_cnt >= RCB_RESET_TRY_TIMES)
dev_err(q->dev->dev, "port%d reset ring fail\n",
hns_ae_get_vf_cb(q->handle)->port_index);
}
/**
*hns_xgmac_config_pad_and_crc - set xgmac pad and crc enable the same time
*@mac_drv: mac driver
*@newval:enable of pad and crc
*/
static void hns_xgmac_config_pad_and_crc(void *mac_drv, u8 newval)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
u32 origin = dsaf_read_dev(drv, XGMAC_MAC_CONTROL_REG);
dsaf_set_bit(origin, XGMAC_CTL_TX_PAD_B, !!newval);
dsaf_set_bit(origin, XGMAC_CTL_TX_FCS_B, !!newval);
dsaf_set_bit(origin, XGMAC_CTL_RX_FCS_B, !!newval);
dsaf_write_dev(drv, XGMAC_MAC_CONTROL_REG, origin);
}
static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
{
u32 tx_ctrl;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
}
/**
* ppe_init_hw - init ppe
* @ppe_cb: ppe device
*/
static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
{
struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
u32 port = ppe_cb->index;
struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
int i;
/* get default RSS key */
netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
mdelay(10);
dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
/* clr and msk except irq*/
hns_ppe_exc_irq_en(ppe_cb, 0);
if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
} else {
hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
}
hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
hns_ppe_cnt_clr_ce(ppe_cb);
if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
hns_ppe_set_vlan_strip(ppe_cb, 0);
dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
HNS_PPEV2_MAX_FRAME_LEN);
/* set default RSS key in h/w */
hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
/* Set default indrection table in h/w */
for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
ppe_cb->rss_indir_table[i] = i;
hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
}
}
/**
* hns_ppe_set_qid - set ppe qid
* @ppe_common: ppe common device
* @qid: queue id
*/
static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
{
u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
PPE_CFG_QID_MODE_DEF_QID_S)) {
dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
PPE_CFG_QID_MODE_DEF_QID_S, qid);
dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
}
}
/**
*hns_xgmac_set_tx_auto_pause_frames - set tx pause param about xgmac
*@mac_drv: mac driver
*@enable:enable tx pause param
*/
static void hns_xgmac_set_tx_auto_pause_frames(void *mac_drv, u16 enable)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
dsaf_set_dev_bit(drv, XGMAC_MAC_PAUSE_CTRL_REG,
XGMAC_PAUSE_CTL_TX_B, !!enable);
/*if enable is not zero ,set tx pause time */
if (enable)
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_TIME_REG, enable);
}
/**
*hns_rcb_ring_init - init rcb ring
*@ring_pair: ring pair control block
*@ring_type: ring type, RX_RING or TX_RING
*/
static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)
{
struct hnae_queue *q = &ring_pair->q;
struct hnae_ring *ring =
(ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;
dma_addr_t dma = ring->desc_dma_addr;
if (ring_type == RX_RING) {
dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
(u32)dma);
dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
(u32)((dma >> 31) >> 1));
hns_rcb_set_rx_ring_bs(q, ring->buf_size);
dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
ring_pair->port_id_in_comm);
dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
ring_pair->port_id_in_comm);
} else {
static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
u32 tx_pause_en)
{
u32 pause_en;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
}
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
u32 full_duplex)
{
u32 tx_ctrl;
struct mac_driver *drv = (struct mac_driver *)mac_drv;
dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
GMAC_DUPLEX_TYPE_B, !!full_duplex);
switch (speed) {
case MAC_SPEED_10:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
break;
case MAC_SPEED_100:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
break;
case MAC_SPEED_1000:
dsaf_set_dev_field(
drv, GMAC_PORT_MODE_REG,
GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
break;
default:
dev_err(drv->dev,
"hns_gmac_adjust_link fail, speed%d mac%d\n",
speed, drv->mac_id);
return -EINVAL;
}
tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1);
dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1);
dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
GMAC_MODE_CHANGE_EB_B, 1);
return 0;
}
/**
*hns_rcb_ring_enable_hw - enable ring
*@ring: rcb ring
*/
void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)
{
dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
}
/**
*hns_rcb_common_init_commit_hw - make rcb common init completed
*@rcb_common: rcb common device
*/
void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)
{
wmb(); /* Sync point before breakpoint */
dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
wmb(); /* Sync point after breakpoint */
}
/**
* hns_ppe_set_port_mode - set port mode
* @ppe_device: ppe device
* @mode: port mode
*/
static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
enum ppe_port_mode mode)
{
dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
}
/**
*hns_xgmac_config_max_frame_length - set xgmac max frame length
*@mac_drv: mac driver
*@newval:xgmac max frame length
*/
static void hns_xgmac_config_max_frame_length(void *mac_drv, u16 newval)
{
struct mac_driver *drv = (struct mac_driver *)mac_drv;
dsaf_write_dev(drv, XGMAC_MAC_MAX_PKT_SIZE_REG, newval);
}
static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
{
dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
}
