int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) { int ret = 0; struct mipi_dsi_cmd *cm; int i = 0; char pload[256]; uint32_t off; /* Align pload at 8 byte boundry */ off = pload; off &= 0x07; if (off) off = 8 - off; off += pload; cm = cmds; for (i = 0; i < count; i++) { memcpy((void *)off, (cm->payload), cm->size); writel(off, DSI_DMA_CMD_OFFSET); writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build dsb(); ret += dsi_cmd_dma_trigger_for_panel(); udelay(80); cm++; } return ret; }
int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) { int ret = 0; struct mipi_dsi_cmd *cm; int i = 0; char pload[256]; uint32_t off; /* Align pload at 8 byte boundry */ off = pload; off &= 0x07; if (off) off = 8 - off; off += pload; cm = cmds; for (i = 0; i < count; i++) { /* Wait for VIDEO_MODE_DONE */ ret = mdss_dsi_wait4_video_done(); if (ret) goto mipi_cmds_error; memcpy((void *)off, (cm->payload), cm->size); arch_clean_invalidate_cache_range((addr_t)(off), size); writel(off, DSI_DMA_CMD_OFFSET); writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build dsb(); ret += dsi_cmd_dma_trigger_for_panel(); dsb(); if (cm->wait) mdelay(cm->wait); else udelay(80); cm++; } mipi_cmds_error: return ret; }