/* CLOCKS */
static void core_dump_clocks(struct seq_file *s)
{
	int i;
	struct clk *clocks[5] = {
		core.dss_ick,
		core.dss1_fck,
		core.dss2_fck,
		core.dss_54m_fck,
		core.dss_96m_fck
	};

	seq_printf(s, "- CORE -\n");

	seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
	seq_printf(s, "mainclk count\t\t%u\n", dss_get_mainclk_state());

	for (i = 0; i < 5; i++) {
		if (!clocks[i])
			continue;
		seq_printf(s, "%-15s\t%lu\t%d\n",
				clocks[i]->name,
				clk_get_rate(clocks[i]),
				clocks[i]->usecount);
	}
}
static int omap_dss_set_manager(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr)
{
	if (!mgr)
		return -EINVAL;

	if (ovl->manager) {
		DSSERR("overlay '%s' already has a manager '%s'\n",
				ovl->name, ovl->manager->name);
		return -EINVAL;
	}

	if (ovl->info.enabled) {
		DSSERR("overlay has to be disabled to change the manager\n");
		return -EINVAL;
	}

	ovl->manager = mgr;

	/* do not set channel out if DSS is off */
	if (!dss_get_mainclk_state()) {
		DSSERR("DSS clock not active, setting ovl manager failed\n");
		return -EIO;
	}

	dispc_set_channel_out(ovl->id, mgr->id);

	return 0;
}
Exemple #3
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static void dss_debug_dump_clocks(struct seq_file *s)
{
	core_dump_clocks(s);
	if (dss_get_mainclk_state()) {
		dss_dump_clocks(s);
		dispc_dump_clocks(s);
	}
#ifdef CONFIG_OMAP2_DSS_DSI
#endif
}
Exemple #4
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static int omap_dss_set_manager(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr)
{
	if (!mgr)
		return -EINVAL;

	if (ovl->manager) {
		dump_stack();
		DSSERR("overlay '%s' already has a manager '%s'\n",
				ovl->name, ovl->manager->name);
		return -EINVAL;
	}

	if (ovl->info.enabled) {
		DSSERR("overlay has to be disabled to change the manager\n");
		return -EINVAL;
	}

	ovl->manager = mgr;

	/* do not set channel out if DSS is off */
	if (!dss_get_mainclk_state())
		return 0;

	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
	/* XXX: on manual update display, in auto update mode, a bug happens
	 * here. When an overlay is first enabled on LCD, then it's disabled,
	 * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
	 * errors. Waiting before changing the channel_out fixes it. I'm
	 * guessing that the overlay is still somehow being used for the LCD,
	 * but I don't understand how or why. */
	msleep(40);
	dispc_set_channel_out(ovl->id, mgr->id);
	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);

	return 0;
}
Exemple #5
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static int omap4_mpu_set_rate(struct device *dev, unsigned long rate)
{
#ifdef CONFIG_OMAP4_KEEP_STATIC_DEPENDENCIES

    int ret;

    ret = clk_set_rate(dpll_mpu_clk, rate);
    if (ret) {
        dev_warn(dev, "%s: Unable to set rate to %ld\n",
                 __func__, rate);
        return ret;
    }

    return 0;
#else
#if 0
    int 	ret = 0;
    unsigned long irqflags = 0;
    u32 reg =OMAP4430_MEMIF_STATDEP_MASK;

    //printk("func=%s, rate =%ld, name=%s\n", __func__, rate, dev->driver->name);

    // rate 300M , LCD off
    //if (rate == 300000000 && cosmo_panel_suspend_flag ==1)
    if (dss_get_mainclk_state() == 0)
    {
        ret = clk_set_rate(dpll_mpu_clk, rate);
        if (ret) {
            dev_warn(dev, "%s: Unable to set rate to %ld\n",
                     __func__, rate);
            return ret;
        }

        if(old_mpu_rate != rate)
        {
            spin_lock_irqsave(&mpu_lock, irqflags);
            cm_rmw_mod_reg_bitsEx(reg, 0, OMAP4430_PRM_MPU_MOD, OMAP4_CM_MPU_STATICDEP_OFFSET);
            spin_unlock_irqrestore(&mpu_lock, irqflags);
        }
        old_mpu_rate= rate;
    }
    else
    {
        if(old_mpu_rate != rate)
        {
            spin_lock_irqsave(&mpu_lock, irqflags);
            cm_rmw_mod_reg_bitsEx(reg, 1, OMAP4430_PRM_MPU_MOD, OMAP4_CM_MPU_STATICDEP_OFFSET);
            spin_unlock_irqrestore(&mpu_lock, irqflags);
        }

        ret = clk_set_rate(dpll_mpu_clk, rate);
        if (ret) {
            dev_warn(dev, "%s: Unable to set rate to %ld\n",
                     __func__, rate);
            return ret;
        }

        old_mpu_rate= rate;
    }
#else
    int ret;

    ret = clk_set_rate(dpll_mpu_clk, rate);
    if (ret) {
        dev_warn(dev, "%s: Unable to set rate to %ld\n",
                 __func__, rate);
        return ret;
    }

#endif

    return 0;
#endif
}