/* U-Boot USB control interface */
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
uint32_t snpsid;
int i, j;
root_hub_devnum = 0;
snpsid = readl(®s->gsnpsid);
printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
(snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
return -ENODEV;
}
dwc_otg_core_init(regs);
dwc_otg_core_host_init(regs);
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
DWC2_HPRT0_PRTOVRCURRCHNG,
DWC2_HPRT0_PRTRST);
mdelay(50);
clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
DWC2_HPRT0_PRTRST);
for (i = 0; i < MAX_DEVICE; i++) {
for (j = 0; j < MAX_ENDPOINT; j++)
bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
}
return 0;
}
int dwc_peripheral_start(void *data, bool enable)
{
struct gadget_wrapper *d;
d = gadget_wrapper;
pr_info("usb: %s d->vbus=%d, enable=%d\n", __func__, d->vbus, enable);
mutex_lock(&udc_lock);
d->vbus = enable;
if ( !d->softconnect )
{
printk("usb: %s , d->softconnect is %d / udc don't start now \r\n",__func__, d->softconnect );
mutex_unlock(&udc_lock);
return 0;
}
if(enable) {
wake_lock(&usb_wake_lock);
udc_enable();
dwc_otg_core_init(GET_CORE_IF(d->pcd));
dwc_otg_enable_global_interrupts(GET_CORE_IF(d->pcd));
dwc_otg_core_dev_init(GET_CORE_IF(d->pcd));
d->udc_startup = 1;
} else {
dwc_otg_disable_global_interrupts(GET_CORE_IF(d->pcd));
dwc_otg_clear_all_int(GET_CORE_IF(d->pcd));
dwc_otg_pcd_stop(d->pcd);
udc_disable();
d->udc_startup = 0;
wake_unlock(&usb_wake_lock);
}
mutex_unlock(&udc_lock);
return 0;
}
/*
* U-Boot USB interface
*/
int usb_lowlevel_init(int index, void **controller)
{
/*
* We need doubleword-aligned buffers for DMA transfers
*/
allocated_buffer = (uint8_t *)malloc(DWC_OTG_HCD_STATUS_BUF_SIZE + DWC_OTG_HCD_DATA_BUF_SIZE + 8);
uint32_t addr = (uint32_t)allocated_buffer;
aligned_buffer = (uint8_t *) ((addr + 7) & ~7);
status_buffer = (uint8_t *)((uint32_t)aligned_buffer + DWC_OTG_HCD_DATA_BUF_SIZE);
int i, j;
hprt0_data_t hprt0 = {.d32 = 0 };
root_hub_devnum = 0;
memset(&g_core_if, 0, sizeof(g_core_if));
dwc_otg_cil_init(&g_core_if, (uint32_t *)CONFIG_SYS_USB_ADDRESS);
if ((g_core_if.snpsid & 0xFFFFF000) !=
0x4F542000) {
printf("SNPSID is invalid (not DWC OTG device): %08x\n", g_core_if.snpsid);
return -1;
}
dwc_otg_core_init(&g_core_if);
dwc_otg_core_host_init(&g_core_if);
hprt0.d32 = dwc_otg_read_hprt0(&g_core_if);
hprt0.b.prtrst = 1;
dwc_write_reg32(g_core_if.host_if->hprt0, hprt0.d32);
mdelay(50);
hprt0.b.prtrst = 0;
dwc_write_reg32(g_core_if.host_if->hprt0, hprt0.d32);
for (i = 0; i < MAX_DEVICE; i++) {
for (j = 0; j < MAX_ENDPOINT; j++) {
control_data_toggle[i][j] = DWC_OTG_HC_PID_DATA1;
bulk_data_toggle[i][j] = DWC_OTG_HC_PID_DATA0;
}
}
return 0;
}
int usb_lowlevel_stop(int index)
{
free(allocated_buffer);
return 0;
}
static void __udc_startup(void)
{
struct gadget_wrapper *d;
d = gadget_wrapper;
pr_info("USB:startup udc\n");
if (!d->udc_startup) {
wake_lock(&usb_wake_lock);
udc_enable();
dwc_otg_core_init(GET_CORE_IF(d->pcd));
dwc_otg_enable_global_interrupts(GET_CORE_IF(d->pcd));
dwc_otg_core_dev_init(GET_CORE_IF(d->pcd));
d->udc_startup = 1;
}
}
int dwc_core_init()
{
int32_t snpsid;
snpsid = dwc_read_reg32(DWC_REG_GSNPSID);
if ((snpsid & 0xFFFFF000) != 0x4F542000) {
ERR("Bad value for SNPSID: 0x%08x\n", snpsid);
return -1;
}
ERR("dwc core init is ok!\n");// show printf is ok.
/*
* Disable the global interrupt until all the interrupt
* handlers are installed.
*/
gahbcfg_data_t ahbcfg = {.d32 = 0 };
ahbcfg.b.glblintrmsk = 1; /* Enable interrupts bit */
dwc_modify_reg32(DWC_REG_GAHBCFG, ahbcfg.d32, 0);
/*
* Initialize the DWC_otg core.
*/
dwc_otg_core_init();
dwc_modify_reg32(DWC_REG_DCTL,0,2);// Disconnect data line
dwc_otg_pcd_init();
dwc_modify_reg32(DWC_REG_DCTL,2,0);// Connect data line
/*
* Enable the global interrupt after all the interrupt
* handlers are installed.
*/
dwc_otg_enable_global_interrupts();
return 0;
}
int
dwc_otg_irq()
{
dwc_common_irq();
dwc_pcd_irq();
return 0;
}
/*
* This function is called when an lm_device is bound to a
* dwc_otg_driver. It creates the driver components required to
* control the device (CIL, HCD, and PCD) and it initializes the
* device. The driver components are stored in a dwc_otg_device
* structure. A reference to the dwc_otg_device is saved in the
* lm_device. This allows the driver to access the dwc_otg_device
* structure on subsequent calls to driver methods for this device.
*
*/
int usb_driver_init(uint32_t base_addr)
{
int retval = 0;
__DWC_WARN("dwc_otg_driver_init\n");
dwc_otg_device = &static_data->dwc_otg_device_inst;
DWC_MEMSET(dwc_otg_device, 0, sizeof(*dwc_otg_device));
/*
* Initialize driver data to point to the global DWC_otg
* Device structure.
*/
__DWC_ERROR("dwc_otg_device addr = 0x%p\n", dwc_otg_device);
dwc_otg_device->core_if = dwc_otg_cil_init(base_addr);
if (!dwc_otg_device->core_if) {
__DWC_ERROR("CIL initialization failed!\n");
retval = -DWC_E_NO_MEMORY;
goto fail;
}
#ifdef USB_DEBUG
/*
* Attempt to ensure this device is really a DWC_otg Controller.
* Read and verify the SNPSID register contents. The value should be
* 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
* as in "OTG version 2.XX" or "OTG version 3.XX".
*/
if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
0x4F542000)
&& ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
0x4F543000)) {
__DWC_WARN("Bad value for SNPSID: 0x%x\n",
dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
retval = -DWC_E_INVALID;
goto fail;
}
#endif /* USB_DEBUG */
/*
* Disable the global interrupt until all the interrupt
* handlers are installed.
*/
__DWC_WARN("USB INIT: Disabling global IRQ\n");
dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
/*
* Initialize the DWC_otg core.
*/
__DWC_WARN("USB INIT: Initializing OTG core\n");
dwc_otg_core_init(dwc_otg_device->core_if);
/*
* Initialize the PCD
*/
__DWC_WARN("USB INIT: Initializing PCD\n");
retval = pcd_init(dwc_otg_device);
if (retval != 0) {
__DWC_ERROR("pcd_init failed\n");
dwc_otg_device->pcd = NULL;
goto fail;
}
__DWC_WARN("USB INIT: Enabling global IRQ\n");
dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
__DWC_WARN("DWC core initialized! \n");
return 0;
fail:
__DWC_ERROR("ERROR! unable to init USB driver\n");
return retval;
}
void w_conn_id_status_change(void *p)
{
dwc_otg_core_if_t *core_if = p;
uint32_t count = 0;
gotgctl_data_t gotgctl = {.d32 = 0 };
gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = B_PERIPHERAL;
#if defined(CONFIG_BATTERY_NXE2000)
otgid_power_control_by_dwc(0);
#elif defined(CONFIG_KP_AXP22)
axp_otg_power_control(0);
#endif
dwc_otg_set_prtpower(core_if, 0);
core_if->host_flag = 0;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_pcd_start(core_if);
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
core_if->host_flag = 1;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_hcd_start(core_if);
}
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
{
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk_data_t gintmsk = {.d32 = 0 };
gintsts_data_t gintsts = {.d32 = 0 };
gintmsk.b.sofintr = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL,
" ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
DWC_SPINUNLOCK(core_if->lock);
/*
* Need to schedule a work, as there are possible DELAY function calls
* Release lock before scheduling workq as it holds spinlock during scheduling
*/
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
core_if, "connection id status change");
DWC_SPINLOCK(core_if->lock);
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
{
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("SRP: Device mode\n");
} else {
hprt0_data_t hprt0;
DWC_PRINTF("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
hprt0.b.prtpwr = 1;
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
cil_hcd_session_start(core_if);
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
void w_wakeup_detected(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32 = 0 };
#if 0
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
#endif //0
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
// dwc_mdelay(70);
hprt0.b.prtres = 0; /* Resume */
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
DWC_READ_REG32(core_if->host_if->hprt0));
cil_hcd_resume(core_if);
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY,
"++Resume and Remote Wakeup Detected Interrupt++\n");
DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
if (dwc_otg_is_device_mode(core_if)) {
dctl_data_t dctl = {.d32 = 0 };
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
dsts));
if (core_if->lx_state == DWC_OTG_L2) {
#ifdef PARTIAL_POWER_DOWN
if (core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32 = 0 };
power.d32 = DWC_READ_REG32(core_if->pcgcctl);
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
power.d32);
power.b.stoppclk = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
}
#endif
/* Clear the Remote Wakeup Signaling */
dctl.b.rmtwkupsig = 1;
DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
dctl, dctl.d32, 0);
DWC_SPINUNLOCK(core_if->lock);
if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
}
DWC_SPINLOCK(core_if->lock);
} else {
glpmcfg_data_t lpmcfg;
lpmcfg.d32 =
DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
lpmcfg.b.hird_thres &= (~(1 << 4));
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
lpmcfg.d32);
}
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
} else {
if (core_if->lx_state != DWC_OTG_L1) {
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
} else {
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
}
static int __devinit dwc_otg_driver_probe(struct platform_device *ofdev)
{
int retval;
struct dwc_otg_device *dwc_dev;
struct device *dev = &ofdev->dev;
struct resource res;
ulong gusbcfg_addr;
u32 usbcfg = 0;
struct resource *nres = 0;
#ifdef CONFIG_OF
u32 prop;
u32 prop_array[15];
#endif
dwc_dev = kzalloc(sizeof(*dwc_dev), GFP_KERNEL);
if (!dwc_dev) {
dev_err(dev, "kmalloc of dwc_otg_device failed\n");
retval = -ENOMEM;
goto fail_dwc_dev;
}
/* Retrieve the memory and IRQ resources. */
dwc_dev->irq = platform_get_irq(ofdev, 0);
if (dwc_dev->irq == NO_IRQ) {
dev_err(dev, "no device irq\n");
retval = -ENODEV;
goto fail_of_irq;
}
nres = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
res = *nres;
if(nres == 0) {
dev_err(dev, "%s: Can't get USB-OTG register address\n",
__func__);
retval = -ENOMEM;
goto fail_of_irq;
}
dwc_dev->phys_addr = res.start;
dwc_dev->base_len = res.end - res.start + 1;
if (!request_mem_region(dwc_dev->phys_addr,
dwc_dev->base_len, dwc_driver_name)) {
dev_err(dev, "request_mem_region failed\n");
retval = -EBUSY;
goto fail_of_irq;
}
/* Map the DWC_otg Core memory into virtual address space. */
dwc_dev->base = ioremap(platform_get_resource(ofdev, IORESOURCE_MEM, 0)->start, SZ_256K);
if (!dwc_dev->base) {
dev_err(dev, "ioremap() failed\n");
retval = -ENOMEM;
goto fail_ioremap;
}
dev_dbg(dev, "mapped base=0x%08x\n", (__force u32)dwc_dev->base);
/*
* Initialize driver data to point to the global DWC_otg
* Device structure.
*/
dev_set_drvdata(dev, dwc_dev);//driver
dwc_dev->core_if =
dwc_otg_cil_init(dwc_dev->base, &dwc_otg_module_params);
if (!dwc_dev->core_if) {
dev_err(dev, "CIL initialization failed!\n");
retval = -ENOMEM;
goto fail_cil_init;
}
/*
* Set the wqfunc of this core_if as "not set"
*/
dwc_dev->core_if->wqfunc_setup_done = 0;
/*
* Validate parameter values after dwc_otg_cil_init.
*/
if (check_parameters(dwc_dev->core_if)) {
retval = -EINVAL;
goto fail_check_param;
}
#ifdef CONFIG_OF
if(!of_property_read_u32(ofdev->dev.of_node,
"dma-mask", (u32*)&dwc_otg_dma_mask)) {
dev->dma_mask = &dwc_otg_dma_mask;
}
else {
dev->dma_mask = NULL;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"ulpi-ddr", &prop)) {
dwc_otg_module_params.phy_ulpi_ddr = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-rx-fifo-size", &prop)) {
dwc_otg_module_params.host_rx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"dev-rx-fifo-size", &prop)) {
dwc_otg_module_params.dev_rx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-nperio-tx-fifo-size", &prop)) {
dwc_otg_module_params.host_nperio_tx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"dev-nperio-tx-fifo-size", &prop)) {
dwc_otg_module_params.dev_nperio_tx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-perio-tx-fifo-size", &prop)) {
dwc_otg_module_params.host_perio_tx_fifo_size = prop;
}
if(!of_property_read_u32_array(ofdev->dev.of_node,
"dev-perio-tx-fifo-size", prop_array, MAX_PERIO_FIFOS)) {
int i;
for(i=0; i<MAX_PERIO_FIFOS; i++)
dwc_otg_module_params.dev_tx_fifo_size[i]
= prop_array[i];
}
if(!of_property_read_u32_array(ofdev->dev.of_node,
"dev-tx-fifo-size", prop_array, MAX_TX_FIFOS)) {
int i;
for(i=0; i<MAX_TX_FIFOS; i++)
dwc_otg_module_params.dev_perio_tx_fifo_size[i]
= prop_array[i];
}
#endif
usb_nop_xceiv_register();
dwc_dev->core_if->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (!dwc_dev->core_if->xceiv) {
retval = -ENODEV;
goto fail_xceiv;
}
dwc_set_feature(dwc_dev->core_if);
/* Initialize the DWC_otg core. */
dwc_otg_core_init(dwc_dev->core_if);
/*
* Disable the global interrupt until all the interrupt
* handlers are installed.
*/
spin_lock(&dwc_dev->lock);
dwc_otg_disable_global_interrupts(dwc_dev->core_if);
spin_unlock(&dwc_dev->lock);
/*
* Install the interrupt handler for the common interrupts before
* enabling common interrupts in core_init below.
*/
retval = request_irq(dwc_dev->irq, dwc_otg_common_irq,
IRQF_SHARED, "dwc_otg", dwc_dev);
if (retval) {
dev_err(dev, "request of irq%d failed retval: %d\n",
dwc_dev->irq, retval);
retval = -EBUSY;
goto fail_req_irq;
} else {
dwc_dev->common_irq_installed = 1;
}
if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
//if (dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY)) {
/* Initialize the PCD */
retval = dwc_otg_pcd_init(dev);
if (retval) {
dev_err(dev, "dwc_otg_pcd_init failed\n");
dwc_dev->pcd = NULL;
goto fail_req_irq;
}
}
gusbcfg_addr = (ulong) (dwc_dev->core_if->core_global_regs)
+ DWC_GUSBCFG;
if (!dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY)) {
//if (dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
/* Initialize the HCD and force_host_mode */
usbcfg = dwc_reg_read(gusbcfg_addr, 0);
usbcfg |= DWC_USBCFG_FRC_HST_MODE;
dwc_reg_write(gusbcfg_addr, 0, usbcfg);
retval = dwc_otg_hcd_init(dev, dwc_dev);
if (retval) {
dev_err(dev, "dwc_otg_hcd_init failed\n");
dwc_dev->hcd = NULL;
goto fail_hcd;
}
/* configure chargepump interrupt */
dwc_dev->hcd->cp_irq = platform_get_irq_byname(ofdev, "chargepumpirq");
if(dwc_dev->hcd->cp_irq != -ENXIO) {
retval = request_irq(dwc_dev->hcd->cp_irq,
dwc_otg_externalchgpump_irq,
IRQF_SHARED,
"dwc_otg_ext_chg_pump", dwc_dev);
if (retval) {
dev_err(dev,
"request of irq failed retval: %d\n",
retval);
retval = -EBUSY;
goto fail_hcd;
} else {
dev_dbg(dev, "%s: ExtChgPump Detection "
"IRQ registered\n", dwc_driver_name);
}
}
}
/*
* Enable the global interrupt after all the interrupt
* handlers are installed.
*/
dwc_otg_enable_global_interrupts(dwc_dev->core_if);
#if 0
usbcfg = dwc_reg_read(gusbcfg_addr, 0);
usbcfg &= ~DWC_USBCFG_FRC_HST_MODE;
dwc_reg_write(gusbcfg_addr, 0, usbcfg);
#endif
return 0;
fail_hcd:
free_irq(dwc_dev->irq, dwc_dev);
if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
if (dwc_dev->pcd)
dwc_otg_pcd_remove(dev);
}
fail_req_irq:
usb_put_phy(dwc_dev->core_if->xceiv);
fail_xceiv:
usb_nop_xceiv_unregister();
fail_check_param:
dwc_otg_cil_remove(dwc_dev->core_if);
fail_cil_init:
dev_set_drvdata(dev, NULL);
iounmap(dwc_dev->base);
fail_ioremap:
release_mem_region(dwc_dev->phys_addr, dwc_dev->base_len);
fail_of_irq:
kfree(dwc_dev);
fail_dwc_dev:
return retval;
}
void w_conn_id_status_change(void *p)
{
dwc_otg_core_if_t *core_if = p;
uint32_t count = 0;
gotgctl_data_t gotgctl = {.d32 = 0 };
gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
#ifdef CONFIG_USB_OTG_UTILS
if (core_if->xceiver->otg->set_vbus)
core_if->xceiver->otg->set_vbus(core_if->xceiver->otg, false);
#endif
core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_pcd_start(core_if);
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_hcd_start(core_if);
}
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
{
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk_data_t gintmsk = {.d32 = 0 };
gintsts_data_t gintsts = {.d32 = 0 };
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL,
" ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
/*
* Need to schedule a work, as there are possible DELAY function calls
*/
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
core_if, "connection id status change");
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
{
hprt0_data_t hprt0;
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("SRP: Device mode\n");
} else {
DWC_PRINTF("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
hprt0.b.prtpwr = 1;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
#ifdef CONFIG_USB_OTG
if (core_if->core_params->otg_supp_enable) {
/* Schedule a work item to init the core */
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_init_core,
core_if, "SRP detected");
} else
#endif
{
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within connection wait timeout */
cil_hcd_session_start(core_if);
}
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
void w_wakeup_detected(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32 = 0 };
#if 0
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
#endif /*0 */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
/* dwc_mdelay(70); */
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
dwc_read_reg32(core_if->host_if->hprt0));
cil_hcd_resume(core_if);
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
void w_a_periph_done(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
if (core_if->op_state == A_PERIPHERAL) {
/* Clear the a_peripheral flag, back to a_host. */
cil_pcd_stop(core_if);
cil_hcd_start(core_if);
core_if->op_state = A_HOST;
}
}
void w_peri_suspend_powersaving(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
if (core_if) {
/* Clear DWC Core interrupts before PHY suspend,
this is because to prevent DWC core Hangs while
accessing some registers with PHY suspended if at
all we get some core interrupts when phy in suspend*/
/* Clear any pending OTG Interrupts */
dwc_write_reg32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
/* Clear any pending interrupts */
dwc_write_reg32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
dwc_otg_disable_global_interrupts(core_if);
/* Suspend trasceiver */
usb_phy_set_suspend(core_if->xceiver, 1);
}
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *
_core_if)
{
uint32_t count = 0;
gintsts_data_t gintsts = {.d32 = 0};
gintmsk_data_t gintmsk = {.d32 = 0};
gotgctl_data_t gotgctl = {.d32 = 0};
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL,
" ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(_core_if) ? "Host" : "Device"));
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(_core_if)) {
DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if) ? "Host" :
"Peripheral"));
MDELAY(100);
if (++count > 10000)
*(uint32_t *) NULL = 0;
}
_core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
pcd_start(_core_if);
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(_core_if)) {
DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if) ? "Host" :
"Peripheral"));
MDELAY(100);
if (++count > 10000)
*(uint32_t *) NULL = 0;
}
_core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
hcd_start(_core_if);
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * _core_if)
{
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
hprt0_data_t hprt0;
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if)) {
DWC_PRINT("SRP: Device mode\n");
} else {
DWC_PRINT("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0(_core_if);
hprt0.b.prtpwr = 1;
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
hcd_session_start(_core_if);
}
#endif /* */
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * _core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY,"++Resume and Remote Wakeup Detected Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if)) {
dctl_data_t dctl = {.d32 = 0};
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts));
#ifdef PARTIAL_POWER_DOWN
if (_core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32 = 0};
power.d32 = dwc_read_reg32(_core_if->pcgcctl);
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
power.b.stoppclk = 0;
dwc_write_reg32(_core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
dwc_write_reg32(_core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
dwc_write_reg32(_core_if->pcgcctl, power.d32);
}
#endif /* */
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dctl,
dctl.d32, 0);
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
_core_if->pcd_cb->resume_wakeup(_core_if->pcd_cb->p);
}
} else {
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32 = 0};
pcgcctl_data_t pcgcctl = {.d32 = 0};
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
UDELAY(10);
/* Now wait for 70 ms. */
hprt0.d32 = dwc_otg_read_hprt0(_core_if);
DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
MDELAY(70);
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
dwc_read_reg32(_core_if->host_if->hprt0));
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.wkupintr = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device has been disconnected from
* the root port.
*/
int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * _core_if)
{
gintsts_data_t gintsts;
printk(KERN_ERR " Disconnect Detected Interrupt++ (%s) %s\n",
(dwc_otg_is_host_mode(_core_if) ? "Host" : "Device"),
op_state_str(_core_if));
DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
(dwc_otg_is_host_mode(_core_if) ? "Host" : "Device"),
op_state_str(_core_if));
/** @todo Consolidate this if statement. */
#ifndef DWC_HOST_ONLY
if (_core_if->op_state == B_HOST) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect(_core_if);
pcd_start(_core_if);
_core_if->op_state = B_PERIPHERAL;
} else if (dwc_otg_is_device_mode(_core_if)) {
gotgctl_data_t gotgctl = {.d32 = 0};
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
if (gotgctl.b.hstsethnpen == 1) {
/* Do nothing, if HNP in process the OTG
* interrupt "Host Negotiation Detected"
* interrupt will do the mode switch.
*/
} else if (gotgctl.b.devhnpen == 0) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect(_core_if);
pcd_start(_core_if);
_core_if->op_state = B_PERIPHERAL;
} else {
DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
}
} else {
if (_core_if->op_state == A_HOST) {
/* A-Cable still connected but device disconnected. */
hcd_disconnect(_core_if);
}
}
#endif /* */
gintsts.d32 = 0;
gintsts.b.disconnect = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that SUSPEND state has been detected on
* the USB.
*
* For HNP the USB Suspend interrupt signals the change from
* "a_peripheral" to "a_host".
*
* When power management is enabled the core will be put in low power
* mode.
*/
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * _core_if)
{
dsts_data_t dsts;
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
if (dwc_otg_is_device_mode(_core_if)) {
/* Check the Device status register to determine if the Suspend
* state is active. */
dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts);
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
"HWCFG4.power Optimize=%d\n", dsts.b.suspsts,
_core_if->hwcfg4.b.power_optimiz);
#ifdef PARTIAL_POWER_DOWN
/** @todo Add a module parameter for power management. */
if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32 = 0};
DWC_DEBUGPL(DBG_CIL, "suspend\n");
power.b.pwrclmp = 1;
dwc_write_reg32(_core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 1;
dwc_modify_reg32(_core_if->pcgcctl, 0, power.d32);
power.b.stoppclk = 1;
dwc_modify_reg32(_core_if->pcgcctl, 0, power.d32);
} else {
DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
}
#endif /* */
/* PCD callback for suspend. */
pcd_suspend(_core_if);
} else {
if (_core_if->op_state == A_PERIPHERAL) {
