Exemple #1
0
static void __init
mpc85xx_setup_pci1(struct pci_controller *hose)
{
	volatile struct ccsr_pci *pci;
	volatile struct ccsr_guts *guts;
	unsigned short temps;
	bd_t *binfo = (bd_t *) __res;

	pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
		    MPC85xx_PCI1_SIZE);

	guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
		    MPC85xx_GUTS_SIZE);

	early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
	temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);

#define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
	if (guts->pordevsr & PORDEVSR_PCI) {
 		early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 	} else {
		/* PCI-X init */
		temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
		early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
	}

	/* Disable all windows (except powar0 since its ignored) */
	pci->powar1 = 0;
	pci->powar2 = 0;
	pci->powar3 = 0;
	pci->powar4 = 0;
	pci->piwar1 = 0;
	pci->piwar2 = 0;
	pci->piwar3 = 0;

	/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
	pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
	pci->potear1 = 0x00000000;
	pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
	/* Enable, Mem R/W */
	pci->powar1 = 0x80044000 |
	   (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);

	/* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
	pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
	pci->potear2 = 0x00000000;
	pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
	/* Enable, IO R/W */
	pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);

	/* Setup 2G inbound Memory Window @ 0 */
	pci->pitar1 = 0x00000000;
	pci->piwbar1 = 0x00000000;
	pci->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local
					   Mem, Snoop R/W, 2G */
}
Exemple #2
0
void __init
mpc83xx_setup_pci2(struct pci_controller *hose)
{
    u16 reg16;
    volatile immr_pcictrl_t * pci_ctrl;
    volatile immr_ios_t * ios;
    bd_t *binfo = (bd_t *) __res;

    pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
    ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));

    /*
     * Configure PCI Outbound Translation Windows
     */
    ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
    ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
    ios->pocmr3 = POCMR_EN | POCMR_DST |
                  (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
                                   MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);

    /* mapped to PCI2 IO space */
    ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
    ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
    ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
                  (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
                                   MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);

    /*
     * Configure PCI Inbound Translation Windows
     */
    pci_ctrl->pitar1 = 0x0;
    pci_ctrl->pibar1 = 0x0;
    pci_ctrl->piebar1 = 0x0;
    pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;

    /*
     * Release PCI RST signal
     */
    pci_ctrl->gcr = 0;
    udelay(2000);
    pci_ctrl->gcr = 1;
    udelay(2000);

    reg16 = 0xff;
    early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);

    /*
     * Clear non-reserved bits in status register.
     */
    early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
    early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);

    iounmap(pci_ctrl);
    iounmap(ios);
}
Exemple #3
0
void sg8100_cardbus_fixup(struct pci_controller *hose, int current_bus, int pci_devfn)
{
	unsigned long ba;
	unsigned int scr, mfr;
	unsigned short bcr;
	unsigned char dc;

	/* Leave the cardbus slots in the reset state for now */
	bcr = 0x0340;
	early_write_config_word(hose, current_bus, pci_devfn, 0x3e, bcr);

	/* Set to use serialized interrupts - the power on default */
	dc = 0x66;
	early_write_config_byte(hose, current_bus, pci_devfn, 0x92, dc);

	/* Enable MFUNC0 to be interrupt source for slot */
	scr = 0x28449060;
	early_write_config_dword(hose, current_bus, pci_devfn, 0x80, scr);

	mfr = 0x00001002;
	early_write_config_dword(hose, current_bus, pci_devfn, 0x8c, mfr);

	/* Turn of power to cardbus slot */
	ba = 0;
	early_read_config_dword(hose, current_bus, pci_devfn, PCI_BASE_ADDRESS_0, &ba);
	if (ba) {
		/* Request power off on cardbus slot */
		writel(0, ba+0x4); /* MASK */
		writel(0, ba+0x10); /* CONTROL */
	}
}
static void __init
sandpoint_setup_winbond_83553(struct pci_controller *hose)
{
	int		devfn;

	/*
	 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
	 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
	 * woule interfere with the PMC's INTC# and INTD# lines.
	 */
	/*
	 * Winbond Fcn 0
	 */
	devfn = PCI_DEVFN(11,0);

	early_write_config_byte(hose,
				0,
				devfn,
				0x43, /* IDE Interrupt Routing Control */
				0xef);
	early_write_config_word(hose,
				0,
				devfn,
				0x44, /* PCI Interrupt Routing Control */
				0x0000);

	/* Want ISA memory cycles to be forwarded to PCI bus */
	early_write_config_byte(hose,
				0,
				devfn,
				0x48, /* ISA-to-PCI Addr Decoder Control */
				0xf0);

	/* Enable Port 92.  */
	early_write_config_byte(hose,
				0,
				devfn,
				0x4e,	/* AT System Control Register */
				0x06);
	/*
	 * Winbond Fcn 1
	 */
	devfn = PCI_DEVFN(11,1);

	/* Put IDE controller into native mode. */
	early_write_config_byte(hose,
				0,
				devfn,
				0x09,	/* Programming interface Register */
				0x8f);

	/* Init IRQ routing, enable both ports, disable fast 16 */
	early_write_config_dword(hose,
				0,
				devfn,
				0x40,	/* IDE Control/Status Register */
				0x00ff0011);
	return;
}
Exemple #5
0
/**
 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
 */
void __init xilinx_pci_init(void)
{
	struct pci_controller *hose;
	struct resource r;
	void __iomem *pci_reg;
	struct device_node *pci_node;

	pci_node = of_find_matching_node(NULL, xilinx_pci_match);
	if(!pci_node)
		return;

	if (of_address_to_resource(pci_node, 0, &r)) {
		pr_err("xilinx-pci: cannot resolve base address\n");
		return;
	}

	hose = pcibios_alloc_controller(pci_node);
	if (!hose) {
		pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
		return;
	}

	/* Setup config space */
	setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
			   r.start + XPLB_PCI_DATA,
			   PPC_INDIRECT_TYPE_SET_CFG_TYPE);

	/* According to the xilinx plbv46_pci documentation the soft-core starts
	 * a self-init when the bus master enable bit is set. Without this bit
	 * set the pci bus can't be scanned.
	 */
	early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);

	/* Set the max latency timer to 255 */
	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);

	/* Set the max bus number to 255 */
	pci_reg = of_iomap(pci_node, 0);
	out_8(pci_reg + XPLB_PCI_BUS, 0xff);
	iounmap(pci_reg);

	/* Nothing past the root bridge is working right now.  By default
	 * exclude config access to anything except bus 0 */
	if (!ppc_md.pci_exclude_device)
		ppc_md.pci_exclude_device = xilinx_pci_exclude_device;

	/* Register the host bridge with the linux kernel! */
	pci_process_bridge_OF_ranges(hose, pci_node, 1);

	pr_info("xilinx-pci: Registered PCI host bridge\n");
}
Exemple #6
0
static void __init
mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 lower_mem,
		   u32 upper_mem, u32 io_base)
{
	volatile struct ccsr_pcie *pcie;
	u16 cmd;
	bd_t *binfo = (bd_t *) __res;

	pcie = ioremap(binfo->bi_immr_base + pcie_offset,
		MPC86xx_PCIE_SIZE);

	early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
	cmd |=  PCI_COMMAND_SERR   | PCI_COMMAND_MASTER |
		PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
	early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);

	/* Disable all windows (except pcieowar0 since its ignored) */
	pcie->pcieowar1 = 0;
	pcie->pcieowar2 = 0;
	pcie->pcieowar3 = 0;
	pcie->pcieowar4 = 0;
	pcie->pcieiwar1 = 0;
	pcie->pcieiwar1 = 0;
	pcie->pcieiwar2 = 0;
	pcie->pcieiwar3 = 0;

	/* Setup Phys:PCIE 1:1 outbound mem window @ MPC86XX_PCIEn_LOWER_MEM */
	pcie->pcieotar1 = (lower_mem >> 12) & 0x000fffff;
	pcie->pcieotear1 = 0x00000000;
	pcie->pcieowbar1 = (lower_mem >> 12) & 0x000fffff;
	/* Enable, Mem R/W */
	pcie->pcieowar1 = 0x80044000 |
		(__ilog2(upper_mem - lower_mem + 1) - 1);

	/* Setup outbound IO windows @ MPC86XX_PCIEn_IO_BASE */
	pcie->pcieotar2 = (MPC86XX_PCIE_LOWER_IO >> 12) & 0x000fffff;
	pcie->pcieotear2 = 0x00000000;
	pcie->pcieowbar2 = (io_base >> 12) & 0x000fffff;
	/* Enable, IO R/W */
	pcie->pcieowar2 = 0x80088000 | (__ilog2(MPC86XX_PCIE_IO_SIZE) - 1);

	/* Setup 2G inbound Memory Window @ 0 */
	pcie->pcieitar1 = 0x00000000;
	pcie->pcieiwbar1 = 0x00000000;
	/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
	pcie->pcieiwar1 = 0xa0f5501e;
}
Exemple #7
0
static void __init
mpc85xx_setup_pci2(struct pci_controller *hose)
{
	volatile struct ccsr_pci *pci;
	unsigned short temps;
	bd_t *binfo = (bd_t *) __res;

	pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
		    MPC85xx_PCI2_SIZE);

	early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
	temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
	early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);

	/* Disable all windows (except powar0 since its ignored) */
	pci->powar1 = 0;
	pci->powar2 = 0;
	pci->powar3 = 0;
	pci->powar4 = 0;
	pci->piwar1 = 0;
	pci->piwar2 = 0;
	pci->piwar3 = 0;

	/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
	pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
	pci->potear1 = 0x00000000;
	pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
	/* Enable, Mem R/W */
	pci->powar1 = 0x80044000 |
	   (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);

	/* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
	pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;
	pci->potear2 = 0x00000000;
	pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
	/* Enable, IO R/W */
	pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);

	/* Setup 2G inbound Memory Window @ 0 */
	pci->pitar1 = 0x00000000;
	pci->piwbar1 = 0x00000000;
	pci->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local
					   Mem, Snoop R/W, 2G */
}
Exemple #8
0
void __init
lopec_setup_winbond_83553(struct pci_controller *hose)
{
	int devfn;

	devfn = PCI_DEVFN(11,0);

	/* IDE interrupt routing (primary 14, secondary 15) */
	early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
	/* PCI interrupt routing */
	early_write_config_word(hose, 0, devfn, 0x44, 0x0000);

	/* ISA-PCI address decoder */
	early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);

	/* RTC, kb, not used in PPC */
	early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
	early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
	devfn = PCI_DEVFN(11, 1);
	early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
	early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
}
static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
					     void __iomem *reg,
					     const struct resource *res)
{
	resource_size_t size = res->end - res->start + 1;
	u32 sa;

	/* Calculate window size */
	sa = (0xffffffffu << ilog2(size)) | 1;
	sa |= 0x1;

	/* RAM is always at 0 local for now */
	writel(0, reg + PCIL0_PTM1LA);
	writel(sa, reg + PCIL0_PTM1MS);

	/* Map on PCI side */
	early_write_config_dword(hose, hose->first_busno, 0,
				 PCI_BASE_ADDRESS_1, res->start);
	early_write_config_dword(hose, hose->first_busno, 0,
				 PCI_BASE_ADDRESS_2, 0x00000000);
	early_write_config_word(hose, hose->first_busno, 0,
				PCI_COMMAND, 0x0006);
}
Exemple #10
0
static void __init
katana_setup_bridge(void)
{
	struct pci_controller hose;
	struct mv64x60_setup_info si;
	void __iomem *vaddr;
	int i;
	u32 v;
	u16 val, type;
	u8 save_exclude;

	/*
	 * Some versions of the Katana firmware mistakenly change the vendor
	 * & device id fields in the bridge's pci device (visible via pci
	 * config accesses).  This breaks mv64x60_init() because those values
	 * are used to identify the type of bridge that's there.  Artesyn
	 * claims that the subsystem vendor/device id's will have the correct
	 * Marvell values so this code puts back the correct values from there.
	 */
	memset(&hose, 0, sizeof(hose));
	vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
	setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
		vaddr + MV64x60_PCI0_CONFIG_DATA);
	save_exclude = mv64x60_pci_exclude_bridge;
	mv64x60_pci_exclude_bridge = 0;

	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);

	if (val != PCI_VENDOR_ID_MARVELL) {
		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_SUBSYSTEM_VENDOR_ID, &val);
		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_VENDOR_ID, val);
		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_SUBSYSTEM_ID, &val);
		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_DEVICE_ID, val);
	}

	/*
	 * While we're in here, set the hotswap register correctly.
	 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
	 */
	early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
		MV64360_PCICFG_CPCI_HOTSWAP, &v);
	v &= ~(1<<19);
	v |= ((1<<17) | (1<<22) | (1<<23));
	early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
		MV64360_PCICFG_CPCI_HOTSWAP, v);

	/* While we're at it, grab the bridge type for later */
	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);

	mv64x60_pci_exclude_bridge = save_exclude;
	iounmap(vaddr);

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	si.pci_1.enable_bus = 1;
	si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
	si.pci_1.pci_io.pci_base_hi = 0;
	si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
	si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
	si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_cmd_bits = 0;
	si.pci_1.latency_timer = 0x80;

	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;

		si.pci_1.acc_cntl_options[i] =
			MV64360_PCI_ACC_CNTL_SNOOP_NONE |
			MV64360_PCI_ACC_CNTL_SWAP_NONE |
			MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
			MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;

		si.pci_1.acc_cntl_options[i] =
			MV64360_PCI_ACC_CNTL_SNOOP_WB |
			MV64360_PCI_ACC_CNTL_SWAP_NONE |
			MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
			((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
				MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
				MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
#endif
	}

	/* Lookup PCI host bridges */
	if (mv64x60_init(&bh, &si))
		printk(KERN_WARNING "Bridge initialization failed.\n");

	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = katana_map_irq;
	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;

	mv64x60_set_bus(&bh, 1, 0);
	bh.hose_b->first_busno = 0;
	bh.hose_b->last_busno = 0xff;

	/*
	 * Need to access hotswap reg which is in the pci config area of the
	 * bridge's hose 0.  Note that pcibios_alloc_controller() can't be used
	 * to alloc hose_a b/c that would make hose 0 known to the generic
	 * pci code which we don't want.
	 */
	bh.hose_a = &katana_hose_a;
	setup_indirect_pci_nomap(bh.hose_a,
		bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
		bh.v_base + MV64x60_PCI0_CONFIG_DATA);
}
Exemple #11
0
static void __init
katana_setup_bridge(void)
{
	struct pci_controller hose;
	struct mv64x60_setup_info si;
	void __iomem *vaddr;
	int i;
	u16 val;
	u8 save_exclude;

	/*
	 * Some versions of the Katana firmware mistakenly change the vendor
	 * & device id fields in the bridge's pci device (visible via pci
	 * config accesses).  This breaks mv64x60_init() because those values
	 * are used to identify the type of bridge that's there.  Artesyn
	 * claims that the subsystem vendor/device id's will have the correct
	 * Marvell values so this code puts back the correct values from there.
	 */
	memset(&hose, 0, sizeof(hose));
	vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
	setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
		vaddr + MV64x60_PCI0_CONFIG_DATA);
	save_exclude = mv64x60_pci_exclude_bridge;
	mv64x60_pci_exclude_bridge = 0;

	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);

	if (val != PCI_VENDOR_ID_MARVELL) {
		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_SUBSYSTEM_VENDOR_ID, &val);
		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_VENDOR_ID, val);
		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_SUBSYSTEM_ID, &val);
		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
			PCI_DEVICE_ID, val);
	}

	mv64x60_pci_exclude_bridge = save_exclude;
	iounmap(vaddr);

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	si.pci_1.enable_bus = 1;
	si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
	si.pci_1.pci_io.pci_base_hi = 0;
	si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
	si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
	si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_cmd_bits = 0;
	si.pci_1.latency_timer = 0x80;

	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
	}

	/* Lookup PCI host bridges */
	if (mv64x60_init(&bh, &si))
		printk(KERN_WARNING "Bridge initialization failed.\n");

	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = katana_map_irq;
	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;

	mv64x60_set_bus(&bh, 1, 0);
	bh.hose_b->first_busno = 0;
	bh.hose_b->last_busno = 0xff;
}