/* Note: this routine returns extra data bits for size detection. */
int __devinit tulip_read_eeprom(long ioaddr, int location, int addr_len)
{
int i;
unsigned retval = 0;
long ee_addr = ioaddr + CSR9;
int read_cmd = location | (EE_READ_CMD << addr_len);
outl(EE_ENB & ~EE_CS, ee_addr);
outl(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outl(EE_ENB | dataval, ee_addr);
eeprom_delay();
outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
}
outl(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
outl(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outl(EE_ENB & ~EE_CS, ee_addr);
return retval;
}
static int __devinit read_eeprom(long ioaddr, int location)
{
int i;
int retval = 0;
long ee_addr = ioaddr + EECTL;
int read_cmd = location |
(inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
outl(EE_ENB & ~EE_CS, ee_addr);
outl(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 12; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
outl(EE_ENB | dataval, ee_addr);
eeprom_delay();
outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
}
outl(EE_ENB, ee_addr);
for (i = 16; i > 0; i--) {
outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
outl(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outl(EE_ENB & ~EE_CS, ee_addr);
return retval;
}
static int read_eeprom(int location)
{
int i;
unsigned int retval = 0;
long ee_addr = ioaddr + Cfg9346;
int read_cmd = location | EE_READ_CMD;
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 10; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
eeprom_delay();
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
}
outb(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
outb(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outb(~EE_CS, ee_addr);
return retval;
}
static int read_eeprom(long ioaddr, int location, int addr_len) {
int i;
unsigned retval = 0;
long ee_addr = ioaddr + Cfg9346;
int read_cmd = location | (EE_READ_CMD << addr_len);
outp(ee_addr, EE_ENB & ~EE_CS);
outp(ee_addr, EE_ENB);
// Shift the read command bits out
for (i = 4 + addr_len; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outp(ee_addr, EE_ENB | dataval);
eeprom_delay();
outp(ee_addr, EE_ENB | dataval | EE_SHIFT_CLK);
eeprom_delay();
}
outp(ee_addr, EE_ENB);
eeprom_delay();
for (i = 16; i > 0; i--) {
outp(ee_addr, EE_ENB | EE_SHIFT_CLK);
eeprom_delay();
retval = (retval << 1) | ((inp(ee_addr) & EE_DATA_READ) ? 1 : 0);
outp(ee_addr, EE_ENB);
eeprom_delay();
}
// Terminate the EEPROM access
outp(ee_addr, ~EE_CS);
return retval;
}
static int eeprom_read(long addr, int location)
{
int i;
int retval = 0;
int ee_addr = addr + EECtrl;
int read_cmd = location | EE_ReadCmd;
writel(EE_ChipSelect, ee_addr);
for (i = 10; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
writel(dataval, ee_addr);
eeprom_delay(ee_addr);
writel(dataval | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
}
writel(EE_ChipSelect, ee_addr);
for (i = 16; i > 0; i--) {
writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
retval = (retval << 1) | ((readl(ee_addr) & EE_DataIn) ? 1 : 0);
writel(EE_ChipSelect, ee_addr);
eeprom_delay(ee_addr);
}
writel(0, ee_addr);
return retval;
}
/******************************************************************************
*
* eeprom_send_addr - send the read address to the '557 serial eeprom
*
*/
static int eeprom_send_addr (unsigned long pci_base,
unsigned char eeprom_addr)
{
register int i;
/* Do each address bit, MSB => LSB - after each address bit is
sent, read the EEDO bit on the '557 to check for the "dummy 0 bit"
which when set to 0, indicates that the address field is complete */
for (i = 5; i >= 0; i--)
{
/* If this bit is a 1, set SDA high. If 0, set it low */
if (eeprom_addr & (1 << i))
set_sda_line (pci_base, HIGH);
else
set_sda_line (pci_base, LOW);
eeprom_delay (DATA_IN_SETUP_TIME); /* Data setup before raising clock */
set_scl_line (pci_base, HIGH); /* Clock in this data bit */
eeprom_delay (SK_HIGH_PERIOD);
set_scl_line (pci_base, LOW); /* Prepare for next bit */
eeprom_delay (SK_LOW_PERIOD);
/* check to see if "dummy 0 bit" is set to 0 indicating address
complete */
if (get_sda_line (pci_base) == LOW)
break; /* address complete */
}
return (OK);
}
/* Note: this routine returns extra data bits for size detection. */
int __devinit tulip_read_eeprom(struct net_device *dev, int location, int addr_len)
{
int i;
unsigned retval = 0;
struct tulip_private *tp = dev->priv;
void __iomem *ee_addr = tp->base_addr + CSR9;
int read_cmd = location | (EE_READ_CMD << addr_len);
iowrite32(EE_ENB & ~EE_CS, ee_addr);
iowrite32(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
iowrite32(EE_ENB | dataval, ee_addr);
eeprom_delay();
iowrite32(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
}
iowrite32(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
iowrite32(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
iowrite32(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
iowrite32(EE_ENB & ~EE_CS, ee_addr);
return (tp->flags & HAS_SWAPPED_SEEPROM) ? swab16(retval) : retval;
}
/*
Write one bit data to Phy Controller
*/
static void phy_write_1bit(u32 ee_addr, u32 phy_data)
{
whereami("phy_write_1bit\n");
outl(phy_data, ee_addr); /* MII Clock Low */
eeprom_delay();
outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
eeprom_delay();
outl(phy_data, ee_addr); /* MII Clock Low */
eeprom_delay();
}
static int recv_bits(int bits) {
int res = 0;
while (bits--) {
res <<= 1;
mask32(HW_GPIO1OUT, 0, GP_EEP_CLK);
eeprom_delay();
mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
eeprom_delay();
res |= !!(read32(HW_GPIO1IN) & GP_EEP_MISO);
}
return res;
}
static void send_bits(int b, int bits) {
while (bits--) {
if (b & (1 << bits))
mask32(HW_GPIO1OUT, 0, GP_EEP_MOSI);
else
mask32(HW_GPIO1OUT, GP_EEP_MOSI, 0);
eeprom_delay();
mask32(HW_GPIO1OUT, 0, GP_EEP_CLK);
eeprom_delay();
mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
eeprom_delay();
}
}
/******************************************************************************
*
* eeprom_send_start - send a start bit with a read opcode to the '557 serial
* eeprom
*
*/
static int eeprom_send_start (unsigned long pci_base, int command)
{
int op_code[2];
switch (command)
{
case EEPROM_WRITE:
op_code[0] = LOW;
op_code[1] = HIGH;
break;
case EEPROM_READ:
op_code[0] = HIGH;
op_code[1] = LOW;
break;
case EEPROM_ERASE:
op_code[0] = HIGH;
op_code[1] = HIGH;
break;
case EEPROM_EWEN:
case EEPROM_EWDS:
op_code[0] = LOW;
op_code[1] = LOW;
break;
default:
return(EEPROM_INVALID_CMD);
}
set_scl_line (pci_base, LOW);
set_sda_line (pci_base, HIGH); /* start bit */
eeprom_delay (DATA_IN_SETUP_TIME);
set_scl_line (pci_base, HIGH); /* clock high */
eeprom_delay (SK_HIGH_PERIOD);
set_scl_line (pci_base, LOW); /* clock low */
eeprom_delay (SK_LOW_PERIOD);
/* send the opcode */
set_sda_line (pci_base, op_code[0]); /* MSB of opcode */
eeprom_delay (DATA_IN_SETUP_TIME);
set_scl_line (pci_base, HIGH); /* clock high */
eeprom_delay (SK_HIGH_PERIOD);
set_scl_line (pci_base, LOW); /* clock low */
eeprom_delay (SK_LOW_PERIOD);
set_sda_line (pci_base, op_code[1]); /* LSB of opcode */
eeprom_delay (DATA_IN_SETUP_TIME);
set_scl_line (pci_base, HIGH); /* clock high */
eeprom_delay (SK_HIGH_PERIOD);
set_scl_line (pci_base, LOW); /* clock low */
eeprom_delay (SK_LOW_PERIOD);
return (OK);
}
/*
Read one bit phy data from PHY controller
*/
static int phy_read_1bit(u32 ee_addr)
{
int phy_data;
whereami("phy_read_1bit\n");
outl(0x50000, ee_addr);
eeprom_delay();
phy_data=(inl(ee_addr)>>19) & 0x1;
outl(0x40000, ee_addr);
eeprom_delay();
return phy_data;
}
u_int32_t
eeprom_get_byte (long addr)
{
u_int32_t input;
u_int32_t data;
int count;
/* Start the Reading of DATA
**
** The first read is a dummy as the data is latched in the
** EPLD and read on the next read access to the EEPROM.
*/
input = pci_read_32 ((u_int32_t *) addr);
data = 0;
count = NUM_OF_BITS;
while (--count >= 0)
{
eeprom_delay ();
input = pci_read_32 ((u_int32_t *) addr);
data <<= 1; /* Shift data over */
data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
}
return data;
}
u_int32_t
eeprom_get_byte (long addr)
{
u_int32_t input;
u_int32_t data;
int count;
/*
*/
input = pci_read_32 ((u_int32_t *) addr);
data = 0;
count = NUM_OF_BITS;
while (--count >= 0)
{
eeprom_delay ();
input = pci_read_32 ((u_int32_t *) addr);
data <<= 1; /* */
data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
}
return data;
}
/*-------------------------------------------------------------
* Function: int eeprom_read ()
*
* Action: Read data from the eeprom, place it at p_data
*
* Returns: OK if read worked, EEPROM_NOT_RESPONDING if
* read fails.
*-------------------------------------------------------------*/
int eeprom_read (unsigned long pci_base,/* PCI Base address */
int eeprom_addr, /* word offset from start of eeprom */
unsigned short *p_data,/* where to put data in memory */
int nwords /* number of 16bit words to read */
)
{
int status; /* result code */
int i; /* loop variable */
/*
* Make sure caller isn't requesting a read beyond the end of the
* eeprom.
*/
if ((eeprom_addr + nwords) > EEPROM_WORD_SIZE)
return (EEPROM_TO_SMALL);
/* Read in desired number of words */
for (i = 0; i < nwords; i++, eeprom_addr++)
{
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
/* Wait CS setup time */
eeprom_delay (SELECT_SETUP_TIME);
/* Send start/read command to begin the read */
if (((status = eeprom_send_start (pci_base, EEPROM_READ)) != OK) ||
/* Send address */
((status = eeprom_send_addr (pci_base, eeprom_addr)) != OK))
return (status);
if ((status = eeprom_get_word (pci_base, p_data++)) != OK)
return (status);
/* De-Select the serial EEPROM */
DESELECT_557_EEP(pci_base);
/* wait the required de-select time between commands */
eeprom_delay (DESELECT_TIME);
}
return (OK);
}
/* Note: this routine returns extra data bits for size detection. */
int tulip_read_eeprom(struct net_device *dev, int location, int addr_len)
{
int i;
unsigned retval = 0;
struct tulip_private *tp = netdev_priv(dev);
void __iomem *ee_addr = tp->base_addr + CSR9;
int read_cmd = location | (EE_READ_CMD << addr_len);
/* If location is past the end of what we can address, don't
* read some other location (ie truncate). Just return zero.
*/
if (location > (1 << addr_len) - 1)
return 0;
iowrite32(EE_ENB & ~EE_CS, ee_addr);
iowrite32(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
iowrite32(EE_ENB | dataval, ee_addr);
eeprom_delay();
iowrite32(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
}
iowrite32(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
iowrite32(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
iowrite32(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
iowrite32(EE_ENB & ~EE_CS, ee_addr);
return (tp->flags & HAS_SWAPPED_SEEPROM) ? swab16(retval) : retval;
}
static int read_eeprom (u16 io_address, int location)
{
int counter;
unsigned return_value = 0;
long eeprom_address = io_address + Config9346;
int read_command = location | EEPROM_READ_COMMAND;
system_port_out_u8 (eeprom_address, EEPROM_ENB & ~EEPROM_CHIP_SELECT);
system_port_out_u8 (eeprom_address, EEPROM_ENB);
/* Shift the read command bits out. */
for (counter = 10; counter >= 0; counter--)
{
int dataval = (read_command & (1 << counter)) ? EEPROM_DATA_WRITE : 0;
system_port_out_u8 (eeprom_address, EEPROM_ENB | dataval);
eeprom_delay ();
system_port_out_u8 (eeprom_address, EEPROM_ENB | dataval |
EEPROM_SHIFT_CLOCK);
eeprom_delay ();
}
system_port_out_u8 (eeprom_address, EEPROM_ENB);
eeprom_delay ();
for (counter = 16; counter > 0; counter--)
{
system_port_out_u8 (eeprom_address, EEPROM_ENB | EEPROM_SHIFT_CLOCK);
eeprom_delay ();
return_value = (return_value << 1) |
((system_port_in_u8 (eeprom_address) & EEPROM_DATA_READ) ? 1 : 0);
system_port_out_u8 (eeprom_address, EEPROM_ENB);
eeprom_delay ();
}
/* Terminate the EEPROM access. */
system_port_out_u8 (eeprom_address, ~EEPROM_CHIP_SELECT);
return return_value;
}
/******************************************************************************
*
* eeprom_get_word - read a 16 bit word from the '557 serial eeprom
*
* Note: this routine assumes that the start/opcode/address have already
* been set up
*/
static int eeprom_get_word (unsigned long pci_base,
unsigned short *word_addr)
{
register int i;
/* Do each data bit, MSB => LSB */
for (i = 15; i >= 0; i--)
{
set_scl_line (pci_base, HIGH);
eeprom_delay (SK_HIGH_PERIOD);
if (get_sda_line (pci_base) == HIGH)
*word_addr |= (1 << i); /* store bit as a '1' */
else
*word_addr &= ~(1 << i); /* store bit as a '0' */
set_scl_line (pci_base, LOW);
eeprom_delay (SK_LOW_PERIOD);
}
return (OK);
}
/******************************************************************************
*
* eeprom_put_word - write a 16 bit word to the '557 serial eeprom
*
* Note: this routine assumes that the start/opcode/address have already
* been set up
*/
static int eeprom_put_word (unsigned long pci_base,
unsigned short data)
{
register int i;
/* Do each data bit, MSB => LSB */
for (i = 15; i >= 0; i--)
{
if (data & (1 << i))
set_sda_line(pci_base, HIGH);
else
set_sda_line(pci_base, LOW);
eeprom_delay (DATA_IN_SETUP_TIME);
set_scl_line (pci_base, HIGH);
eeprom_delay (SK_HIGH_PERIOD);
set_scl_line (pci_base, LOW);
eeprom_delay (SK_LOW_PERIOD);
}
return (OK);
}
static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) {
unsigned retval = 0;
long ee_addr = ioaddr + SCBeeprom;
outpw(ee_addr, EE_ENB | EE_SHIFT_CLK);
// Shift the command bits out
do {
short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
outpw(ee_addr, dataval);
eeprom_delay(ee_addr);
outpw(ee_addr, dataval | EE_SHIFT_CLK);
eeprom_delay(ee_addr);
retval = (retval << 1) | ((inpw(ee_addr) & EE_DATA_READ) ? 1 : 0);
} while (--cmd_len >= 0);
outpw(ee_addr, EE_ENB);
// Terminate the EEPROM access.
outpw(ee_addr, EE_ENB & ~EE_CS);
return retval;
}
int seeprom_read(void *dst, int offset, int size) {
int i;
u16 *ptr = (u16 *)dst;
u16 recv;
if (size & 1)
return -1;
mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
eeprom_delay();
for (i = 0; i < size; i++) {
mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
send_bits((0x600 | (offset + i)), 11);
recv = recv_bits(16);
*ptr++ = recv;
mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
eeprom_delay();
}
return size;
}
static unsigned RtlReadEeprom(rtl8139_t *rtl, unsigned location)
{
int i;
unsigned int retval = 0;
long ee_addr = rtl->iobase + Cfg9346;
int read_cmd = location | EE_READ_CMD;
out(ee_addr, EE_ENB & ~EE_CS);
out(ee_addr, EE_ENB);
/* Shift the read command bits out. */
for (i = 10; i >= 0; i--)
{
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
out(ee_addr, EE_ENB | dataval);
eeprom_delay();
out(ee_addr, EE_ENB | dataval | EE_SHIFT_CLK);
eeprom_delay();
}
out(ee_addr, EE_ENB);
eeprom_delay();
for (i = 16; i > 0; i--)
{
out(ee_addr, EE_ENB | EE_SHIFT_CLK);
eeprom_delay();
retval = (retval << 1) | ((in(ee_addr) & EE_DATA_READ) ? 1 : 0);
out(ee_addr, EE_ENB);
eeprom_delay();
}
/* Terminate the EEPROM access. */
out(ee_addr, ~EE_CS);
return retval;
}
void
eeprom_put_byte (long addr, long data, int count)
{
u_int32_t output;
while (--count >= 0)
{
output = (data & EPROM_ACTIVE_OUT_BIT) ? 1 : 0; /* Get next data bit */
output |= EPROM_ENCS; /* Add Chip Select */
data >>= 1;
eeprom_delay ();
pci_write_32 ((u_int32_t *) addr, output); /* Output it */
}
}
void
eeprom_put_byte (long addr, long data, int count)
{
u_int32_t output;
while (--count >= 0)
{
output = (data & EPROM_ACTIVE_OUT_BIT) ? 1 : 0;
output |= EPROM_ENCS;
data >>= 1;
eeprom_delay ();
pci_write_32 ((u_int32_t *) addr, output);
}
}
/*-------------------------------------------------------------
* Function: int eeprom_write_disable ()
*
* Action: Disable writes to the eeprom
*
* Returns: OK if command sent, EEPROM_NOT_RESPONDING if not.
*
*-------------------------------------------------------------*/
int eeprom_write_disable (unsigned long pci_base)
{
int status; /* result code */
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
/* Wait CS setup time */
eeprom_delay (SELECT_SETUP_TIME);
/* Send start/write enable command */
if (((status = eeprom_send_start (pci_base, EEPROM_EWDS)) != OK) ||
/* Send address */
((status = eeprom_send_addr (pci_base, EEPROM_EWDS_OP)) != OK))
return (status);
/* De-Select the serial EEPROM */
DESELECT_557_EEP(pci_base);
/* wait the required de-select time between commands */
eeprom_delay (DESELECT_TIME);
return (OK);
}
/* Read Serial EEPROM through EEPROM Access Register, Note that location is
in word (16 bits) unit */
static u16 read_eeprom(long ioaddr, int location)
{
int i;
u16 retval = 0;
long ee_addr = ioaddr + mear;
u32 read_cmd = location | EEread;
outl(0, ee_addr);
eeprom_delay();
outl(EECLK, ee_addr);
eeprom_delay();
/* Shift the read command (9) bits out. */
for (i = 8; i >= 0; i--) {
u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
outl(dataval, ee_addr);
eeprom_delay();
outl(dataval | EECLK, ee_addr);
eeprom_delay();
}
outb(EECS, ee_addr);
eeprom_delay();
/* read the 16-bits data in */
for (i = 16; i > 0; i--) {
outl(EECS, ee_addr);
eeprom_delay();
outl(EECS | EECLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outl(0, ee_addr);
eeprom_delay();
outl(EECLK, ee_addr);
return (retval);
}
static u16 sis900_read_eeprom(int location)
{
int i;
u16 retval = 0;
long ee_addr = ioaddr + mear;
u32 read_cmd = location | EEread;
outl(0, ee_addr);
eeprom_delay();
outl(EECLK, ee_addr);
eeprom_delay();
for (i = 8; i >= 0; i--) {
u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
outl(dataval, ee_addr);
eeprom_delay();
outl(dataval | EECLK, ee_addr);
eeprom_delay();
}
outb(EECS, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outl(EECS, ee_addr);
eeprom_delay();
outl(EECS | EECLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
eeprom_delay();
}
outl(0, ee_addr);
eeprom_delay();
outl(EECLK, ee_addr);
return (retval);
}
static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
{
int i;
unsigned retval = 0;
void __iomem *ee_addr = ioaddr + Cfg9346;
int read_cmd = location | (EE_READ_CMD << addr_len);
writeb (EE_ENB & ~EE_CS, ee_addr);
writeb (EE_ENB, ee_addr);
eeprom_delay ();
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
writeb (EE_ENB | dataval, ee_addr);
eeprom_delay ();
writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay ();
}
writeb (EE_ENB, ee_addr);
eeprom_delay ();
for (i = 16; i > 0; i--) {
writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay ();
retval =
(retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
0);
writeb (EE_ENB, ee_addr);
eeprom_delay ();
}
/* Terminate the EEPROM access. */
writeb (~EE_CS, ee_addr);
eeprom_delay ();
return retval;
}
int
read_eeprom(int ioaddr, int location)
{
int i;
unsigned short retval = 0;
short ee_addr = ioaddr + EEPROM_Ctrl;
int read_cmd = location | EE_READ_CMD;
short ctrl_val = EE_CS | _586_RESET;
outb(ctrl_val, ee_addr);
/* Shift the read command bits out. */
for (i = 8; i >= 0; i--) {
short outval = (read_cmd & (1 << i)) ? ctrl_val | EE_DATA_WRITE
: ctrl_val;
outb(outval, ee_addr);
outb(outval | EE_SHIFT_CLK, ee_addr); /* EEPROM clock tick. */
eeprom_delay();
outb(outval, ee_addr); /* Finish EEPROM a clock tick. */
eeprom_delay();
}
outb(ctrl_val, ee_addr);
for (i = 16; i > 0; i--) {
outb(ctrl_val | EE_SHIFT_CLK, ee_addr); eeprom_delay();
retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
outb(ctrl_val, ee_addr); eeprom_delay();
}
/* Terminate the EEPROM access. */
ctrl_val &= ~EE_CS;
outb(ctrl_val | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
outb(ctrl_val, ee_addr);
eeprom_delay();
return retval;
}
static void solo_eeprom_reg_write(struct solo6010_dev *solo_dev, u32 data)
{
solo_reg_write(solo_dev, SOLO_EEPROM_CTRL, data);
eeprom_delay();
}