static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
{
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
write_c0_dtaglo(data);
ehb();
cache_op(Index_Store_Tag_D, CKSEG0 | offset);
ehb();
write_c0_errctl(errctl);
ehb();
}
static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
{
unsigned int data;
unsigned int errctl;
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
cache_op(Index_Load_Tag_D, CKSEG0 | offset);
ehb();
data = read_c0_dtaglo();
ehb();
write_c0_errctl(errctl);
ehb();
return data;
}
static unsigned int ispram_load_tag(unsigned int offset)
{
unsigned int data;
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
cache_op(Index_Load_Tag_I, CKSEG0 | offset);
ehb();
data = read_c0_taglo();
ehb();
write_c0_errctl(errctl);
ehb();
return data;
}
static __cpuinit void ispram_store_data(unsigned int offset, unsigned int datalo, unsigned int datahi)
{
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
#ifdef CONFIG_CPU_BIG_ENDIAN
write_c0_idatalo(datahi);
ehb();
write_c0_idatahi(datalo);
ehb();
#else
write_c0_idatalo(datalo);
ehb();
write_c0_idatahi(datahi);
ehb();
#endif
cache_op(MIPS34K_Index_Store_Data_I, CKSEG0|offset);
ehb();
write_c0_errctl(errctl);
ehb();
}
void disable_brcm_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&brcm_irqlock, flags);
__disable_ack_brcm_irq(irq);
if ((irq == INTERRUPT_ID_SOFTWARE_0) || (irq == INTERRUPT_ID_SOFTWARE_1)) {
clear_c0_status(0x1 << (STATUSB_IP0 + irq - INTERRUPT_ID_SOFTWARE_0));
#if defined(CONFIG_BCM_LOT1) && defined(CONFIG_BCM93383)
ehb();
#endif
}
spin_unlock_irqrestore(&brcm_irqlock, flags);
}
void enable_brcm_irq(unsigned int irq)
{
unsigned long flags;
if( irq == MIPS_TIMER_INT ) {
return;
}
spin_lock_irqsave(&brcm_irqlock, flags);
if( irq >= INTERNAL_ISR_TABLE_OFFSET ) {
irq -= INTERNAL_ISR_TABLE_OFFSET;
*pperf[irq/32].pMask |= (1 << (irq%32));
}
else if ((irq == INTERRUPT_ID_SOFTWARE_0) || (irq == INTERRUPT_ID_SOFTWARE_1)) {
set_c0_status(0x1 << (STATUSB_IP0 + irq - INTERRUPT_ID_SOFTWARE_0));
#if defined(CONFIG_BCM_LOT1) && defined(CONFIG_BCM93383)
ehb();
#endif
}
spin_unlock_irqrestore(&brcm_irqlock, flags);
}
void mask_ack_brcm_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&brcm_irqlock, flags);
__disable_ack_brcm_irq(irq);
#if defined(CONFIG_SMP)
if (irq == INTERRUPT_ID_SOFTWARE_0) {
int this_cpu = smp_processor_id();
int other_cpu = !this_cpu;
per_cpu(ipi_pending, this_cpu) = 0;
mb();
clear_c0_cause(1<<CAUSEB_IP0);
if (per_cpu(ipi_pending, other_cpu)) {
set_c0_cause(1<<CAUSEB_IP0);
}
clear_c0_status(1<<STATUSB_IP0);
}
#else
if (irq == INTERRUPT_ID_SOFTWARE_0) {
clear_c0_status(1<<STATUSB_IP0);
clear_c0_cause(1<<CAUSEB_IP0);
#if defined(CONFIG_BCM_LOT1) && defined(CONFIG_BCM93383)
ehb();
#endif
}
#endif
if (irq == INTERRUPT_ID_SOFTWARE_1) {
clear_c0_status(1<<STATUSB_IP1);
clear_c0_cause(1<<CAUSEB_IP1);
}
spin_unlock_irqrestore(&brcm_irqlock, flags);
}
int scc_reset(enum scc_id id, u32 value)
{
if ((id >= SCC_MAX) || (id < 0))
return -EINVAL;
/* Invert value to the strait logic from the negative hardware logic */
if (value == 0)
value = 1;
else
value = 0;
/* Write the value to the register */
reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value);
/* sync flush */
asm("sync"); /* request bus write queue flush */
ehb(); /* wait until previous bus commit instr has finished */
asm("nop"); /* wait for flush to occur */
asm("nop"); /* wait for flush to occur */
udelay(100);
return 0;
}
