static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask,
u8 tll_channel_count)
{
unsigned reg;
int i;
/* Program the 3 TLL channels upfront */
for (i = 0; i < tll_channel_count; i++) {
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
/* Disable AutoIdle, BitStuffing and use SDR Mode */
reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
}
/* Program Common TLL register */
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
| OMAP_TLL_SHARED_CONF_USB_DIVRATION
| OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
/* Enable channels now */
for (i = 0; i < tll_channel_count; i++) {
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
/* Enable only the reg that is needed */
if (!(tll_channel_mask & 1<<i))
continue;
reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
ehci_omap_writeb(omap->tll_base,
OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
i+1, ehci_omap_readb(omap->tll_base,
OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
}
}
static void omap_usb_utmi_init(struct ehci_hcd_omap *omap)
{
unsigned reg;
int i;
/* Program the 3 TLL channels upfront */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
dev_dbg(&omap->dev->dev,
"port %d: OMAP_TTL_CHANNEL_CONF_%d=%08x\n",
i, i+1, ehci_omap_readl(omap->tll_base,
OMAP_TLL_CHANNEL_CONF(i)));
if (omap->port_data[i].flags & EHCI_HCD_OMAP_FLAG_NOBITSTUFF)
reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
else
reg &= ~OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
if (omap_usb_port_utmi_chanel_config(omap->port_data[i].mode)) {
if (omap->port_data[i].flags
& EHCI_HCD_OMAP_FLAG_AUTOIDLE)
reg |= OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE;
else
reg &= ~OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE;
} else {
if (omap->port_data[i].flags
& EHCI_HCD_OMAP_FLAG_AUTOIDLE)
reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE;
else
reg &= ~OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE;
}
if (omap->port_data[i].mode == EHCI_HCD_OMAP_MODE_ULPI_TLL_DDR)
reg |= OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE;
else
reg &= ~OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE;
ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
}
/* Program Common TLL register */
ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF,
OMAP_TLL_SHARED_CONF_FCLK_IS_ON
| OMAP_TLL_SHARED_CONF_USB_DIVRATION);
/* Enable channels now */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
/* Enable only the reg that is needed */
if (!(omap->port_data[i].flags & EHCI_HCD_OMAP_FLAG_ENABLED))
continue;
reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
if (omap_usb_port_utmi_chanel_config(omap->port_data[i].mode))
reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE(1);
else
reg &= ~OMAP_TLL_CHANNEL_CONF_CHANMODE(3);
reg &= ~(OMAP_TLL_CHANNEL_CONF_FSLSMODE(0xf));
reg |= OMAP_TLL_CHANNEL_CONF_FSLSMODE(
omap_usb_port_fslsmode(omap->port_data[i].mode));
ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
dev_dbg(&omap->dev->dev,
"port %d enabled: OMAP_TTL_CHANNEL_CONF_%d=%08x:%08x\n",
i, i+1, reg, ehci_omap_readl(omap->tll_base,
OMAP_TLL_CHANNEL_CONF(i)));
ehci_omap_writeb(omap->tll_base,
OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
dev_dbg(&omap->dev->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
i+1, ehci_omap_readb(omap->tll_base,
OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
}
}
