int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode, unsigned char phsdir) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (ctrmode > 0x3 || phsdir > 1) return -EINVAL; ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13)); ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK); return 0; }
/* Event Trigger Configuration functions */ int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt, unsigned char prd) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (evt > 0x7 || prd > 0x3) return -EINVAL; ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK); ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK); return 0; }
int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen, unsigned char syncosel) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (phsen > 1 || syncosel > 0x3) return -EINVAL; ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2)); ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS, TBCTL_SYNCOSEL_MASK); return 0; }
int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode, unsigned char ctlmode, unsigned char edgemode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (loadmode > 1 || ctlmode > 1 || edgemode > 3) return -EINVAL; ehrpwm_reg_config(ehrpwm, HRCNFG, loadmode << HRCNFG_LDMD_POS, BIT(3)); ehrpwm_reg_config(ehrpwm, HRCNFG, ctlmode << HRCNFG_CTLMD_POS, BIT(2)); ehrpwm_reg_config(ehrpwm, HRCNFG, edgemode, HRCNFG_EDGEMD_MASK); return 0; }
/* Time Base Module Configurations */ int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv, unsigned char hspclkdiv) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (clkdiv > 0x7 || hspclkdiv > 0x7) return -EINVAL; ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS, TBCTL_CLKDIV_MASK); ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS, TBCTL_HSPCLKDIV_MASK); return 0; }
/* Trip Zone configuration functions */ int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input, enum tz_event evt) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); unsigned short val = 0; unsigned short mask; unsigned short pos; if (evt > 4 || input > 7) return -EINVAL; switch (evt) { case TZ_ONE_SHOT_EVENT: pos = input + 8; mask = BIT((pos)) | BIT(input); ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask); break; case TZ_CYCLE_BY_CYCLE: pos = input; mask = BIT(pos) | BIT((pos + 8)); ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask); break; case TZ_OSHT_CBC: case TZ_DIS_EVT: if (evt == TZ_OSHT_CBC) val = 1; else val = 0; pos = input + 8; mask = BIT((pos)); ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask); pos = input; mask = BIT((pos)); ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask); break; default: dev_dbg(p->dev, "%s: Invalid command", __func__); return -EINVAL; } debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL)); return 0; }
int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (ch > 1) return -EINVAL; if (ch == 0) ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS, BIT(2)); else ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS, BIT(5)); return 0; }
/* Dead Band Configuration functions */ int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode, unsigned char polsel, unsigned char outmode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3) return -EINVAL; ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS, DBCTL_INMODE_MASK); ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS, DBCTL_PLSEL_MASK); ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK); return 0; }
int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch, unsigned char act) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (ch > 1) return -EINVAL; if (ch == 0) ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK); else ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS, AQCSFRC_OUTB_MASK); return 0; }
int ehrpwm_aq_set_one_shot_act(struct pwm_device *p, unsigned char ch, unsigned char act) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (ch > 1 || act > 3) return -EINVAL; if (ch == 0) ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK); else ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS, AQSFRC_ACTB_MASK); return 0; }
int ehrpwm_tb_force_sync(struct pwm_device *p) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6)); return 0; }
/* PWM chopper Configuration functions */ int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty, unsigned char chpfreq, unsigned char oshtwidth) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf) return -EINVAL; ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS, PCCTL_CHPDUTY_MASK); ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS, PCCTL_CHPFREQ_MASK); ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS, PCCTL_OSHTWTH_MASK); return 0; }
inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3)); return 0; }
int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event, unsigned char int_en_dis) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (event == TZ_ONE_SHOT_EVENT) ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis << TZEINT_OSHTEVT_POS, BIT(2)); else if (event == TZ_CYCLE_BY_CYCLE) ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis << TZEINT_CBCEVT_POS, BIT(1)); else return -EINVAL; debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT)); return 0; }
int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch, unsigned char act) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (act > 0x3 || ch > 1) return -EINVAL; if (ch == 0) ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK); else ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS, TZCTL_ACTB_MASK); debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL)); return 0; }
int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (chpen > 1) return -EINVAL; ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0)); return 0; }
int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (loadmode > 0x1) return -EINVAL; ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3)); return 0; }
int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode, unsigned char shdwbmode, unsigned char loadamode, unsigned char loadbmode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 || loadbmode > 0x3) return -EINVAL; ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS, BIT(4)); ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS, BIT(6)); ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK); ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS, CMPCTL_LDBMODE_MASK); return 0; }
int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (loadmode > 0x3) return -EINVAL; ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS, AQSFRC_CFRC_LOAD_MASK); return 0; }
int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode, unsigned char ctlmode, unsigned char edgemode) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); if (loadmode > 1 || ctlmode > 1 || edgemode > 3) return -EINVAL; if (ehrpwm->version == PWM_VERSION_1) { ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG, loadmode << HRCNFG_LDMD_POS, BIT(3)); ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG, ctlmode << HRCNFG_CTLMD_POS, BIT(2)); ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG, edgemode, HRCNFG_EDGEMD_MASK); } else { ehrpwm_reg_config(ehrpwm, HRCNFG, loadmode << HRCNFG_LDMD_POS, BIT(3)); ehrpwm_reg_config(ehrpwm, HRCNFG, ctlmode << HRCNFG_CTLMD_POS, BIT(2)); ehrpwm_reg_config(ehrpwm, HRCNFG, edgemode, HRCNFG_EDGEMD_MASK); } return 0; }
int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg) { struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p); unsigned char reg; if (!cfg) return -EINVAL; if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 || cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 || cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3) return -EINVAL; if (cfg->ch == 0) reg = AQCTLA; else reg = AQCTLB; ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK); ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS, ACTCTL_CPRD_MASK); ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup << ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK); ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown << ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK); ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup << ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK); ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown << ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK); return 0; }