static void pmc_gpe_init(config_t *config) { uint8_t *pmc_regs; uint32_t gpio_cfg; uint32_t gpio_cfg_reg; const uint32_t gpio_cfg_mask = (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | (GPE0_DWX_MASK << GPE0_DW2_SHIFT); pmc_regs = pmc_mmio_regs(); gpio_cfg = 0; /* Route the GPIOs to the GPE0 block. Determine that all values * are different, and if they aren't use the reset values. */ if (config->gpe0_dw0 == config->gpe0_dw1 || config->gpe0_dw1 == config->gpe0_dw2) { printk(BIOS_INFO, "PMC: Using default GPE route.\n"); gpio_cfg = read32(pmc_regs + GPIO_CFG); } else { gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; } gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); /* Set GPE enables based on devictree. */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, config->gpe0_en_3, config->gpe0_en_4); }
static void pch_power_options(void) { u16 reg16; const char *state; /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; /* Get the chip configuration */ config_t *config = dev->chip_info; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* * Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * * If the option is not existent (Laptops), use Kconfig setting. */ /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/ //get_option(&pwr_on, "power_on_after_fail"); pwr_on = MAINBOARD_POWER_ON; reg16 = pci_read_config16(dev, GEN_PMCON_B); reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: reg16 |= 1; state = "off"; break; case MAINBOARD_POWER_ON: reg16 &= ~1; state = "on"; break; case MAINBOARD_POWER_KEEP: reg16 &= ~1; state = "state keep"; break; default: state = "undefined"; } pci_write_config16(dev, GEN_PMCON_B, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, config->gpe0_en_3, config->gpe0_en_4); /* SMI setup based on device tree configuration */ enable_alt_smi(config->ec_smi_gpio, config->alt_gp_smi_en); }
static int pch_power_options(struct udevice *dev) { int pwr_on_after_power_fail = MAINBOARD_POWER_OFF; const char *state; u32 enable[4]; u16 reg16; int ret; dm_pci_read_config16(dev, GEN_PMCON_3, ®16); reg16 &= 0xfffe; switch (pwr_on_after_power_fail) { case MAINBOARD_POWER_OFF: reg16 |= 1; state = "off"; break; case MAINBOARD_POWER_ON: reg16 &= ~1; state = "on"; break; case MAINBOARD_POWER_KEEP: reg16 &= ~1; state = "state keep"; break; default: state = "undefined"; } dm_pci_write_config16(dev, GEN_PMCON_3, reg16); debug("Set power %s after power failure.\n", state); /* GPE setup based on device tree configuration */ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "intel,gpe0-en", enable, ARRAY_SIZE(enable)); if (ret) return -EINVAL; enable_all_gpe(enable[0], enable[1], enable[2], enable[3]); /* SMI setup based on device tree configuration */ enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "intel,alt-gp-smi-enable", 0)); return 0; }
/* Disable all GPE */ void disable_all_gpe(void) { enable_all_gpe(0, 0, 0, 0); }