void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
{
	preempt_disable();
	enable_kernel_spe();
	kvmppc_save_guest_spe(vcpu);
	vcpu->arch.shadow_msr &= ~MSR_SPE;
	preempt_enable();
}
static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
{
	preempt_disable();
	enable_kernel_spe();
	kvmppc_load_guest_spe(vcpu);
	vcpu->arch.shadow_msr |= MSR_SPE;
	preempt_enable();
}
Exemple #3
0
static int pmc_suspend_enter(suspend_state_t state)
{
	int ret = 0;
	int result;

	switch (state) {
#ifdef CONFIG_PPC_85xx
	case PM_SUSPEND_MEM:
#ifdef CONFIG_SPE
		enable_kernel_spe();
#endif
		enable_kernel_fp();

		pr_debug("%s: Entering deep sleep\n", __func__);

		local_irq_disable();
		mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_DPSLP);

		pr_debug("%s: Resumed from deep sleep\n", __func__);
		break;
#endif

	case PM_SUSPEND_STANDBY:
		local_irq_disable();
		flush_dcache_L1();

		setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP);
		/* At this point, the CPU is asleep. */

		/* Upon resume, wait for SLP bit to be clear. */
		result = spin_event_timeout(
			(in_be32(&pmc_regs->powmgtcsr) & POWMGTCSR_SLP) == 0,
			10000, 10);
		if (!result) {
			pr_err("%s: timeout waiting for SLP bit "
				"to be cleared\n", __func__);
			ret = -ETIMEDOUT;
		}
		break;

	default:
		ret = -EINVAL;

	}
	return ret;
}
Exemple #4
0
static int pmc_suspend_enter(suspend_state_t state)
{
	int ret;
	u32 powmgtreq = 0x00500000;

	switch (state) {
	case PM_SUSPEND_MEM:
#ifdef CONFIG_SPE
		enable_kernel_spe();
#endif
		pr_debug("Entering deep sleep\n");

		local_irq_disable();
		mpc85xx_enter_deep_sleep(get_immrbase(),
				powmgtreq);
		pr_debug("Resumed from deep sleep\n");

		return 0;

	/* else fall-through */
	case PM_SUSPEND_STANDBY:
		local_irq_disable();

		/* Start the power monitor using FPGA */
		pixis_start_pm_sleep();

		setbits32(&pmc_regs->pmcsr, PMCSR_SLP);

		/* At this point, the CPU is asleep. */
		/* Upon resume, wait for SLP bit to be clear. */
		ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP)
				== 0, 10000, 10) ? 0 : -ETIMEDOUT;
		if (ret)
			dev_err(pmc_dev,
				"timeout waiting for SLP bit to be cleared\n");
		/* Stop the power monitor using FPGA */
		pixis_stop_pm_sleep();

		return 0;

	default:
		return -EINVAL;

	}

}
static void spe_begin(void)
{
	/* We just start SPE operations and will save SPE registers later. */
	preempt_disable();
	enable_kernel_spe();
}