u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
{
u32 volatile status = 0;
u32 volatile data = 0;
u32 rc = 0;
unsigned long volatile t_start = get_timer(0);
/* We enable mdio gpio purpose register, and disable it when exit. */
enable_mdio(1);
//printf("\n MDIO Read operation!!\n");
// make sure previous read operation is complete
while(1)
{
// 0 : Read/write operation complet
if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
break;
} else if(get_timer(t_start) > (5UL * CFG_HZ)) {
enable_mdio(0);
printf("\n MDIO Read operation is ongoing !!\n");
return rc;
}
}
data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
outw(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
outw(MDIO_PHY_CONTROL_0, data);
//printf("\n Set Command [0x%08X] to PHY 0x%8x!!\n", data, MDIO_PHY_CONTROL_0);
// make sure read operation is complete
t_start = get_timer(0);
while(1)
{
if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
status = inw(MDIO_PHY_CONTROL_0);
*read_data = (u32)(status & 0x0000FFFF);
//printf("\n MDIO_PHY_CONTROL_0: 0x%8x!!\n", status);
enable_mdio(0);
return 1;
}
else if(get_timer(t_start) > (5UL * CFG_HZ))
{
enable_mdio(0);
printf("\n MDIO Read operation is ongoing and Time Out!!\n");
return 0;
}
}
}
u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
{
u32 volatile status = 0;
u32 rc = 0;
unsigned long volatile t_start = jiffies;
u32 volatile data = 0;
/* We enable mdio gpio purpose register, and disable it when exit. */
enable_mdio(1);
// make sure previous read operation is complete
while (1) {
// 0 : Read/write operation complete
if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
break;
}
else if (time_after(jiffies, t_start + 5*HZ)) {
enable_mdio(0);
printk("\n MDIO Read operation is ongoing !!\n");
return rc;
}
}
data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
sysRegWrite(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
sysRegWrite(MDIO_PHY_CONTROL_0, data);
//printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
// make sure read operation is complete
t_start = jiffies;
while (1) {
if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
status = sysRegRead(MDIO_PHY_CONTROL_0);
*read_data = (u32)(status & 0x0000FFFF);
enable_mdio(0);
return 1;
}
else if (time_after(jiffies, t_start+5*HZ)) {
enable_mdio(0);
printk("\n MDIO Read operation is ongoing and Time Out!!\n");
return 0;
}
}
}
u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
{
unsigned long volatile t_start=get_timer(0);
u32 volatile data;
enable_mdio(1);
// make sure previous write operation is complete
while(1)
{
if (!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
break;
}
else if(get_timer(t_start) > (5UL * CFG_HZ))
{
enable_mdio(0);
printf("\n MDIO Write operation is ongoing !!\n");
return 0;
}
}
data = (0x01 << 16) | (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
outw(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
outw(MDIO_PHY_CONTROL_0, data); //start operation
//printf("\n Set Command [0x%08X] to PHY 0x%8x!!\n", data, MDIO_PHY_CONTROL_0);
t_start = get_timer(0);
// make sure write operation is complete
while(1)
{
if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31))) // 0 : Read/write operation complete
{
enable_mdio(0);
return 1;
}
else if(get_timer(t_start) > (5UL * CFG_HZ))
{
enable_mdio(0);
printf("\n MDIO Write operation is ongoing and Time Out!!\n");
return 0;
}
}
}
u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
{
unsigned long volatile t_start=jiffies;
u32 volatile data;
enable_mdio(1);
// make sure previous write operation is complete
while(1) {
if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
break;
}
else if (time_after(jiffies, t_start + 5 * HZ)) {
enable_mdio(0);
printk("\n MDIO Write operation ongoing\n");
return 0;
}
}
data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
sysRegWrite(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
//printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
t_start = jiffies;
// make sure write operation is complete
while (1) {
if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
{
enable_mdio(0);
return 1;
}
else if (time_after(jiffies, t_start + 5 * HZ)) {
enable_mdio(0);
printk("\n MDIO Write operation Time Out\n");
return 0;
}
}
}
u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
{
u32 volatile status = 0;
u32 volatile data = 0;
u32 rc = 0;
unsigned long volatile t_start = get_timer(0);
/* We enable mdio gpio purpose register, and disable it when exit. */
enable_mdio(1);
// make sure previous read operation is complete
while(1)
{
#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
// rd_rdy: read operation is complete
if(!( inw(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
#else
// 0 : Read/write operation complet
if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
#endif
{
break;
}else if(get_timer(t_start) > (5 * CFG_HZ)){
enable_mdio(0);
printf("\n MDIO Read operation is ongoing !!\n");
return rc;
}
}
#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
outw(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
#else
data = (phy_addr << 24) | (phy_register << 16);
outw(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
outw(MDIO_PHY_CONTROL_0, data);
#endif
//printf("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
// make sure read operation is complete
t_start = get_timer(0);
while(1)
{
#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
if( inw(MDIO_PHY_CONTROL_1) & (0x1 << 1))
{
status = inw(MDIO_PHY_CONTROL_1);
*read_data = (u32)(status >>16);
enable_mdio(0);
return 1;
}
#else
if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
{
status = inw(MDIO_PHY_CONTROL_0);
*read_data = (u32)(status & 0x0000FFFF);
enable_mdio(0);
return 1;
}
#endif
else if(get_timer(t_start) > (5 * CFG_HZ))
{
enable_mdio(0);
printf("\n MDIO Read operation is ongoing and Time Out!!\n");
return 0;
}
}
u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
{
u32 volatile status = 0;
u32 rc = 0;
unsigned long volatile t_start = jiffies;
#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3352) && !defined (CONFIG_RALINK_RT5350)
u32 volatile data = 0;
#endif
/* We enable mdio gpio purpose register, and disable it when exit. */
enable_mdio(1);
// make sure previous read operation is complete
while (1) {
#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
// rd_rdy: read operation is complete
if(!( sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
#else
// 0 : Read/write operation complet
if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
#endif
{
break;
}
else if (time_after(jiffies, t_start + 5*HZ)) {
enable_mdio(0);
printk("\n MDIO Read operation is ongoing !!\n");
return rc;
}
}
#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
sysRegWrite(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
#else
data = (phy_addr << 24) | (phy_register << 16);
sysRegWrite(MDIO_PHY_CONTROL_0, data);
data |= (1<<31);
sysRegWrite(MDIO_PHY_CONTROL_0, data);
#endif
//printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
// make sure read operation is complete
t_start = jiffies;
while (1) {
#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)) {
status = sysRegRead(MDIO_PHY_CONTROL_1);
*read_data = (u32)(status >>16);
enable_mdio(0);
return 1;
}
#else
if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
status = sysRegRead(MDIO_PHY_CONTROL_0);
*read_data = (u32)(status & 0x0000FFFF);
enable_mdio(0);
return 1;
}
#endif
else if (time_after(jiffies, t_start+5*HZ)) {
enable_mdio(0);
printk("\n MDIO Read operation is ongoing and Time Out!!\n");
return 0;
}
}