/**
* Handle an event on the NSS pin
*
* A falling edge of NSS indicates that the master is starting a new
* transaction. A rising edge indicates that we have finsihed
*
* @param signal GPIO signal for the NSS pin
*/
void spi_event(enum gpio_signal signal)
{
stm32_dma_chan_t *rxdma;
uint16_t *nss_reg;
uint32_t nss_mask;
uint16_t i;
/* If not enabled, ignore glitches on NSS */
if (!enabled)
return;
/* Check chip select. If it's high, the AP ended a transaction. */
nss_reg = gpio_get_level_reg(GPIO_SPI1_NSS, &nss_mask);
if (REG16(nss_reg) & nss_mask) {
enable_sleep(SLEEP_MASK_SPI);
/*
* If the buffer is still used by the host command, postpone
* the DMA rx setup.
*/
if (state == SPI_STATE_PROCESSING) {
setup_transaction_later = 1;
return;
}
/* Set up for the next transaction */
spi_init(); /* Fix for bug chrome-os-partner:31390 */
return;
}
disable_sleep(SLEEP_MASK_SPI);
/* Chip select is low = asserted */
if (state != SPI_STATE_READY_TO_RX) {
/*
* AP started a transaction but we weren't ready for it.
* Tell AP we weren't ready, and ignore the received data.
*/
CPRINTS("SPI not ready");
tx_status(EC_SPI_NOT_READY);
state = SPI_STATE_RX_BAD;
return;
}
/* We're now inside a transaction */
state = SPI_STATE_RECEIVING;
tx_status(EC_SPI_RECEIVING);
rxdma = dma_get_channel(STM32_DMAC_SPI1_RX);
/* Wait for version, command, length bytes */
if (wait_for_bytes(rxdma, 3, nss_reg, nss_mask))
goto spi_event_error;
if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
/* Protocol version 3 */
struct ec_host_request *r = (struct ec_host_request *)in_msg;
int pkt_size;
/* Wait for the rest of the command header */
if (wait_for_bytes(rxdma, sizeof(*r), nss_reg, nss_mask))
goto spi_event_error;
/*
* Check how big the packet should be. We can't just wait to
* see how much data the host sends, because it will keep
* sending dummy data until we respond.
*/
pkt_size = host_request_expected_size(r);
if (pkt_size == 0 || pkt_size > sizeof(in_msg))
goto spi_event_error;
/* Wait for the packet data */
if (wait_for_bytes(rxdma, pkt_size, nss_reg, nss_mask))
goto spi_event_error;
spi_packet.send_response = spi_send_response_packet;
spi_packet.request = in_msg;
spi_packet.request_temp = NULL;
spi_packet.request_max = sizeof(in_msg);
spi_packet.request_size = pkt_size;
/* Response must start with the preamble */
memcpy(out_msg, out_preamble, sizeof(out_preamble));
spi_packet.response = out_msg + sizeof(out_preamble);
/* Reserve space for the preamble and trailing past-end byte */
spi_packet.response_max = sizeof(out_msg)
- sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH;
spi_packet.response_size = 0;
spi_packet.driver_result = EC_RES_SUCCESS;
/* Move to processing state */
state = SPI_STATE_PROCESSING;
tx_status(EC_SPI_PROCESSING);
host_packet_receive(&spi_packet);
return;
} else if (in_msg[0] >= EC_CMD_VERSION0) {
/*
* Protocol version 2
*
* TODO(crosbug.com/p/20257): Remove once kernel supports
* version 3.
*/
#ifdef CHIP_FAMILY_STM32F0
CPRINTS("WARNING: Protocol version 2 is not supported on the F0"
" line due to crbug.com/31390");
#endif
args.version = in_msg[0] - EC_CMD_VERSION0;
args.command = in_msg[1];
args.params_size = in_msg[2];
/* Wait for parameters */
if (wait_for_bytes(rxdma, 3 + args.params_size,
nss_reg, nss_mask))
goto spi_event_error;
/*
* Params are not 32-bit aligned in protocol version 2. As a
* workaround, move them to the beginning of the input buffer
* so they are aligned.
*/
if (args.params_size)
memmove(in_msg, in_msg + 3, args.params_size);
args.params = in_msg;
args.send_response = spi_send_response;
/* Allow room for the header bytes */
args.response = out_msg + SPI_PROTO2_OFFSET;
args.response_max = sizeof(out_msg) - SPI_PROTO2_OVERHEAD;
args.response_size = 0;
args.result = EC_RES_SUCCESS;
/* Move to processing state */
state = SPI_STATE_PROCESSING;
tx_status(EC_SPI_PROCESSING);
host_command_received(&args);
return;
}
spi_event_error:
/* Error, timeout, or protocol we can't handle. Ignore data. */
tx_status(EC_SPI_RX_BAD_DATA);
state = SPI_STATE_RX_BAD;
CPRINTS("SPI rx bad data");
CPRINTF("in_msg=[");
for (i = 0; i < dma_bytes_done(rxdma, sizeof(in_msg)); i++)
CPRINTF("%02x ", in_msg[i]);
CPRINTF("]\n");
}
enum power_state power_handle_state(enum power_state state)
{
switch (state) {
case POWER_G3:
break;
case POWER_S5:
if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1)
return POWER_S5S3; /* Power up to next state */
break;
case POWER_S3:
/* Check for state transitions */
if (!power_has_signals(IN_PGOOD_S3)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S3S5;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
/* Power up to next state */
return POWER_S3S0;
} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
/* Power down to next state */
return POWER_S3S5;
}
break;
case POWER_S0:
if (!power_has_signals(IN_PGOOD_S0)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S0S3;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
/* Power down to next state */
return POWER_S0S3;
}
break;
case POWER_G3S5:
/* Enable 3.3V DSW */
gpio_set_level(GPIO_PP3300_DSW_EN, 1);
/*
* Wait 10ms after +3VALW good, since that powers VccDSW and
* VccSUS.
*/
msleep(10);
/* Enable PP5000 (5V) rail as 1.05V and 1.2V rails need 5V
* rail to regulate properly. */
gpio_set_level(GPIO_PP5000_EN, 1);
/* Wait for PP1050/PP1200 PGOOD to go LOW to
* indicate that PP5000 is stable */
while ((power_get_signals() & IN_PGOOD_PP5000) != 0) {
if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
CPRINTS("timeout waiting for PP5000");
gpio_set_level(GPIO_PP5000_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
}
/* Turn on 3.3V DSW gated rail for core regulator */
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
/* Assert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 1);
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050 |
IN_PCH_SLP_SUS_DEASSERTED)) {
gpio_set_level(GPIO_PP1050_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
/* Wait 5ms for SUSCLK to stabilize */
msleep(5);
/* Call hook to indicate out of G3 state */
hook_notify(HOOK_CHIPSET_PRE_INIT);
return POWER_S5;
case POWER_S5S3:
/* Turn on power to RAM */
gpio_set_level(GPIO_PP1800_EN, 1);
gpio_set_level(GPIO_PP1200_EN, 1);
if (power_wait_signals(IN_PGOOD_S3)) {
gpio_set_level(GPIO_PP1800_EN, 0);
gpio_set_level(GPIO_PP1200_EN, 0);
chipset_force_shutdown();
return POWER_S5;
}
/*
* Take lightbar out of reset, now that +5VALW is
* available and we won't leak +3VALW through the reset
* line.
*/
gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
/*
* Enable touchpad power so it can wake the system from
* suspend.
*/
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
/* Turn on USB power rail. */
gpio_set_level(GPIO_PP5000_USB_EN, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
return POWER_S3;
case POWER_S3S0:
/* Wait 20ms before allowing VCCST_PGOOD to rise. */
msleep(20);
/* Enable wireless. */
wireless_set_state(WIRELESS_ON);
/* Make sure the touchscreen is on, too. */
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
/* Wait for non-core power rails good */
if (power_wait_signals(IN_PGOOD_S0)) {
chipset_force_shutdown();
wireless_set_state(WIRELESS_OFF);
return POWER_S3;
}
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/*
* Disable idle task deep sleep. This means that the low
* power idle task will not go into deep sleep while in S0.
*/
disable_sleep(SLEEP_MASK_AP_RUN);
/* Wait 99ms after all voltages good */
msleep(99);
/*
* Throttle CPU if necessary. This should only be asserted
* when +VCCP is powered (it is by now).
*/
gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
/* Set PCH_PWROK */
gpio_set_level(GPIO_PCH_PWROK, 1);
gpio_set_level(GPIO_SYS_PWROK, 1);
return POWER_S0;
case POWER_S0S3:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
/* Clear PCH_PWROK */
gpio_set_level(GPIO_SYS_PWROK, 0);
gpio_set_level(GPIO_PCH_PWROK, 0);
/* Wait 40ns */
udelay(1);
/* Suspend wireless */
wireless_set_state(WIRELESS_SUSPEND);
/*
* Enable idle task deep sleep. Allow the low power idle task
* to go into deep sleep in S3 or lower.
*/
enable_sleep(SLEEP_MASK_AP_RUN);
/*
* Deassert prochot since CPU is off and we're about to drop
* +VCCP.
*/
gpio_set_level(GPIO_CPU_PROCHOT, 0);
return POWER_S3;
case POWER_S3S5:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* Disable wireless */
wireless_set_state(WIRELESS_OFF);
/* Disable peripheral power */
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
gpio_set_level(GPIO_PP5000_USB_EN, 0);
/* Turn off power to RAM */
gpio_set_level(GPIO_PP1800_EN, 0);
gpio_set_level(GPIO_PP1200_EN, 0);
/*
* Put touchscreen and lightbar in reset, so we won't
* leak +3VALW through the reset line to chips powered
* by +5VALW.
*
* (Note that we're no longer powering down +5VALW due
* to crosbug.com/p/16600, but to minimize side effects
* of that change we'll still reset these components in
* S5.)
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
return pause_in_s5 ? POWER_S5 : POWER_S5G3;
case POWER_S5G3:
/* Deassert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 0);
/* Turn off power rails enabled in S5 */
gpio_set_level(GPIO_PP1050_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
/* Disable 3.3V DSW */
gpio_set_level(GPIO_PP3300_DSW_EN, 0);
return POWER_G3;
}
return state;
}
static enum power_state _power_handle_state(enum power_state state)
{
int tries = 0;
switch (state) {
case POWER_G3:
break;
case POWER_S5:
if (forcing_shutdown) {
power_button_pch_release();
forcing_shutdown = 0;
}
#ifdef CONFIG_BOARD_HAS_RTC_RESET
/* Wait for S5 exit and attempt RTC reset it supported */
if (power_s5_up)
return power_wait_s5_rtc_reset();
#endif
if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
return POWER_S5S3; /* Power up to next state */
break;
case POWER_S3:
if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S3S5;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
/* Power up to next state */
return POWER_S3S0;
} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
/* Power down to next state */
return POWER_S3S5;
}
break;
case POWER_S0:
if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
chipset_force_shutdown();
return POWER_S0S3;
#ifdef CONFIG_POWER_S0IX
} else if ((gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) &&
(gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) {
return POWER_S0S0ix;
#endif
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
/* Power down to next state */
return POWER_S0S3;
}
break;
#ifdef CONFIG_POWER_S0IX
case POWER_S0ix:
/*
* TODO: add code for unexpected power loss
*/
if ((gpio_get_level(GPIO_PCH_SLP_S0_L) == 1) &&
(gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) {
return POWER_S0ixS0;
}
break;
#endif
case POWER_G3S5:
/* Call hooks to initialize PMIC */
hook_notify(HOOK_CHIPSET_PRE_INIT);
/*
* Allow up to 1s for charger to be initialized, in case
* we're trying to boot the AP with no battery.
*/
while (charge_prevent_power_on(0) &&
tries++ < CHARGER_INITIALIZED_TRIES) {
msleep(CHARGER_INITIALIZED_DELAY_MS);
}
/* Return to G3 if battery level is too low */
if (charge_want_shutdown() ||
tries > CHARGER_INITIALIZED_TRIES) {
CPRINTS("power-up inhibited");
chipset_force_shutdown();
return POWER_G3;
}
if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
chipset_force_shutdown();
return POWER_G3;
}
power_s5_up = 1;
return POWER_S5;
case POWER_S5S3:
if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S5G3;
}
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
return POWER_S3;
case POWER_S3S0:
if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S3S5;
}
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
/* Enable wireless */
wireless_set_state(WIRELESS_ON);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/*
* Disable idle task deep sleep. This means that the low
* power idle task will not go into deep sleep while in S0.
*/
disable_sleep(SLEEP_MASK_AP_RUN);
/*
* Throttle CPU if necessary. This should only be asserted
* when +VCCP is powered (it is by now).
*/
gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
return POWER_S0;
case POWER_S0S3:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
/* Suspend wireless */
wireless_set_state(WIRELESS_SUSPEND);
/*
* Enable idle task deep sleep. Allow the low power idle task
* to go into deep sleep in S3 or lower.
*/
enable_sleep(SLEEP_MASK_AP_RUN);
return POWER_S3;
#ifdef CONFIG_POWER_S0IX
case POWER_S0S0ix:
/* call hooks before standby */
hook_notify(HOOK_CHIPSET_SUSPEND);
lpc_enable_wake_mask_for_lid_open();
/*
* Enable idle task deep sleep. Allow the low power idle task
* to go into deep sleep in S0ix.
*/
enable_sleep(SLEEP_MASK_AP_RUN);
return POWER_S0ix;
case POWER_S0ixS0:
lpc_disable_wake_mask_for_lid_open();
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/*
* Disable idle task deep sleep. This means that the low
* power idle task will not go into deep sleep while in S0.
*/
disable_sleep(SLEEP_MASK_AP_RUN);
return POWER_S0;
#endif
case POWER_S3S5:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* Disable wireless */
wireless_set_state(WIRELESS_OFF);
/* Always enter into S5 state. The S5 state is required to
* correctly handle global resets which have a bit of delay
* while the SLP_Sx_L signals are asserted then deasserted. */
power_s5_up = 0;
return POWER_S5;
case POWER_S5G3:
chipset_force_g3();
return POWER_G3;
default:
break;
}
return state;
}
void usb_interrupt(void)
{
uint32_t status = GR_USB_GINTSTS;
uint32_t oepint = status & GINTSTS(OEPINT);
uint32_t iepint = status & GINTSTS(IEPINT);
int ep;
print_later("interrupt: GINTSTS 0x%08x", status, 0, 0, 0, 0);
/* We can suspend if the host stops talking to us. But if anything else
* comes along (even ERLYSUSP), we should NOT suspend. */
if (status & GINTSTS(USBSUSP)) {
print_later("usb_suspend()", 0, 0, 0, 0, 0);
enable_sleep(SLEEP_MASK_USB_DEVICE);
} else {
disable_sleep(SLEEP_MASK_USB_DEVICE);
}
#ifdef DEBUG_ME
if (status & GINTSTS(ERLYSUSP))
print_later("usb_early_suspend()", 0, 0, 0, 0, 0);
if (status & GINTSTS(WKUPINT))
print_later("usb_wakeup()", 0, 0, 0, 0, 0);
if (status & GINTSTS(ENUMDONE))
print_later("usb_enumdone()", 0, 0, 0, 0, 0);
#endif
if (status & GINTSTS(RESETDET))
usb_resetdet();
if (status & GINTSTS(USBRST))
usb_reset();
/* Endpoint interrupts */
if (oepint || iepint) {
/* Note: It seems that the DAINT bits are only trustworthy for
* identifying interrupts when selected by the corresponding
* OEPINT and IEPINT bits from GINTSTS. */
uint32_t daint = GR_USB_DAINT;
print_later(" oepint%c iepint%c daint 0x%08x",
oepint ? '!' : '_', iepint ? '!' : '_',
daint, 0, 0);
/* EP0 has a combined IN/OUT handler. Only call it once, but
* let it know which direction(s) had an interrupt. */
if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
uint32_t intr_on_out = (oepint &&
(daint & DAINT_OUTEP(0)));
uint32_t intr_on_in = (iepint &&
(daint & DAINT_INEP(0)));
ep0_interrupt(intr_on_out, intr_on_in);
}
/* Invoke the unidirectional IN and OUT functions for the other
* endpoints. Each handler must clear their own bits in
* DIEPINTn/DOEPINTn. */
for (ep = 1; ep < USB_EP_COUNT; ep++) {
if (oepint && (daint & DAINT_OUTEP(ep)))
usb_ep_rx[ep]();
if (iepint && (daint & DAINT_INEP(ep)))
usb_ep_tx[ep]();
}
}
if (status & GINTSTS(GOUTNAKEFF))
GR_USB_DCTL |= DCTL_CGOUTNAK;
if (status & GINTSTS(GINNAKEFF))
GR_USB_DCTL |= DCTL_CGNPINNAK;
GR_USB_GINTSTS = status;
print_later("end of interrupt", 0, 0, 0, 0, 0);
}
