void main(unsigned long bist) { int s3resume = 0; if (bist == 0) enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); early_superio_config(); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); /* This has to happen after i945_early_initialization() */ init_artec_dongle(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }
static void main(unsigned long bist) { unsigned long x; device_t dev; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); w83697hf_set_clksel_48(DUMMY_DEV); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram(); print_debug("Setup CPU Interface\n"); c3_cpu_setup(ctrl.d0f2); ddr_ram_setup(); if (bist == 0) early_mtrr_init(); }
void main(unsigned long bist) { if (bist == 0) { #if 0 enable_lapic(); init_timer(); #endif } winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); #if 0 print_pci_devices(); #endif if (!bios_reset_detected()) { enable_smbus(); #if 0 dump_spd_registers(); dump_smbus_registers(); #endif sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); } #if 0 dump_pci_devices(); dump_pci_device(PCI_DEV(0, 0, 0)); #endif }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
/** * Setup mainboard specific registers pre raminit. */ static void mb_early_setup(void) { /* - Hub Interface to PCI Bridge Registers - */ /* 12-Clock Retry Enable */ pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402); /* Master Latency Timer Count */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); /* I/O Address Base */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0); /* - LPC Interface Bridge Registers - */ /* Delayed Transaction Enable */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002); /* Disable the TCO Timer system reboot feature */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02); /* CPU Frequency Strap */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); /* ACPI base address and enable Resource Indicator */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); /* Enable the SMBUS */ enable_smbus(); /* ACPI base address and disable Resource Indicator */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); /* ACPI Enable */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); }
void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; if (bist == 0) enable_lapic(); /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); nm10_enable_lpc(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); pineview_early_initialization(); post_code(0x30); printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); ram_check(0x200000,0x300000); rcba_config(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* This is needed to be able to call udelay(). It could be moved to * memreset_setup, since udelay is called in memreset. */ init_timer(); // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); }
void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); report_bist_failure(bist); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void mainboard_romstage_entry(unsigned long bist) { /* TODO: It's a PC87364 actually! */ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); report_bist_failure(bist); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { int s3resume = 0, boot_mode = 0; if (bist == 0) enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : boot_mode, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }
void mainboard_romstage_entry(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); report_bist_failure(bist); ddr_ram_setup(&ctrl); }
void main(unsigned long bist) { /* FIXME: It's a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); }
void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); report_bist_failure(bist); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { it8712f_24mhz_clkin(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); }
void main(unsigned long bist) { /* FIXME: Should be PC97307! */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); pch_enable_lpc(); enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); }
void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); enable_mainboard_devices(); ddr_ram_setup(&ctrl); }
static void sio_setup(void) { uint32_t dword; uint8_t byte; enable_smbus(); // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0); dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4); dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword); }
static void main(unsigned long bist) { device_t dev; /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd); /* * Disable the firewire stuff, which apparently steps on IO 0+ on * reset. Doh! */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6305), 0); if (dev != PCI_DEV_INVALID) pci_write_config8(dev, 0x15, 0x1c); enable_vt8235_serial(); console_init(); enable_smbus(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // init_timer(); post_code(0x05); print_debug(" Enabling mainboard devices\n"); enable_mainboard_devices(); print_debug(" Enabling shadow ram\n"); enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); if (bist == 0) early_mtrr_init(); //dump_pci_devices(); }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; u8 s3_resume; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); console_init(); report_bist_failure(bist); enable_smbus(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); if (s3_resume) boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); }
void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; const struct mrc_saved_data *cache; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; if (!mrc_cache_get_current(&cache)) { mp->saved_data_size = cache->size; mp->saved_data = &cache->data[0]; } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (mrc_entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) enable_smbus(); ret = mrc_entry(mp); cbmem_initialize_empty(); printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, mp->data_to_save_size); if (mp->data_to_save != NULL && mp->data_to_save_size > 0) mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); }
void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(SERIAL_DEV, 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
static void main(unsigned long bist) { if (bist == 0) early_mtrr_init(); enable_vt8231_serial(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); vt8231_enable_rom(); enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); /* this is way more generic than we need. sdram_initialize(ARRAY_SIZE(cpu), cpu); */ sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); } post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); post_code(0x32); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. * It would be nice to fixup prink spinlocks for ROM XIP mode. * I think it could be done by putting the spinlock flag in the cache * of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); // Need to use TMICT to synconize FID/VID wants_reset = mcp55_early_setup_x(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } if (wants_reset) printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_khepri_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); }