static int oktagon_dma_read(void *opaque, uint8_t *buf, int len)
{
struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
esp_dma_enable(ncr->devobject.lsistate, 0);
if (ncr->data_valid) {
*buf = ncr->data;
ncr->data_valid = false;
}
return 1;
}
static void esp_gpio_demux(void *opaque, int irq, int level)
{
switch (irq) {
case 0:
parent_esp_reset(opaque, irq, level);
break;
case 1:
esp_dma_enable(opaque, irq, level);
break;
}
}
static int oktagon_dma_write(void *opaque, uint8_t *buf, int len)
{
struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
esp_dma_enable(ncr->devobject.lsistate, 0);
if (!ncr->data_valid) {
ncr->data = *buf;
ncr->data_valid = true;
return 1;
}
return 0;
}
static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
{
trace_esp_pci_dma_start(val);
pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
| DMA_STAT_DONE | DMA_STAT_ABORT
| DMA_STAT_ERROR | DMA_STAT_PWDN);
esp_dma_enable(&pci->esp, 0, 1);
}
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
{
SysBusESPState *sysbus = ESP(opaque);
ESPState *s = &sysbus->esp;
switch (irq) {
case 0:
parent_esp_reset(s, irq, level);
break;
case 1:
esp_dma_enable(opaque, irq, level);
break;
}
}
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
{
DeviceState *d = opaque;
SysBusESPState *sysbus = container_of(d, SysBusESPState, busdev.qdev);
ESPState *s = &sysbus->esp;
switch (irq) {
case 0:
parent_esp_reset(s, irq, level);
break;
case 1:
esp_dma_enable(opaque, irq, level);
break;
}
}
static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
{
trace_esp_pci_dma_idle(val);
esp_dma_enable(&pci->esp, 0, 0);
}
static void ncr9x_io_bput(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val)
{
int reg_shift = 2;
addr &= ncr->board_mask;
if (ncr == &ncr_oktagon2008_scsi[0] || ncr == &ncr_oktagon2008_scsi[1]) {
if (addr == OKTAGON_EEPROM_SCL) {
eeprom_i2c_set(ncr->eeprom, BITBANG_I2C_SCL, (val & 0x80) != 0);
} else if (addr == OKTAGON_EEPROM_SDA) {
eeprom_i2c_set(ncr->eeprom, BITBANG_I2C_SDA, (val & 0x80) != 0);
} else if (addr >= OKTAGON_DMA_START && addr < OKTAGON_DMA_END) {
ncr->data = val;
ncr->data_valid = true;
esp_dma_enable(ncr->devobject.lsistate, 1);
return;
} else if (addr == OKTAGON_INTENA) {
ncr->state = val;
set_irq2_oktagon(ncr);
return;
}
if (addr < OKTAGON_ESP_ADDR || addr >= OKTAGON_ESP_ADDR + 0x100) {
return;
}
reg_shift = 1;
} else if (ncr == &ncr_fastlane_scsi[0] || ncr == &ncr_fastlane_scsi[1]) {
if (addr >= FASTLANE_HARDBITS) {
if (addr == FASTLANE_HARDBITS) {
int oldstate = ncr->state;
ncr->state = val;
if (!(oldstate & FLSC_PB_ENABLE_DMA) && (ncr->state & FLSC_PB_ENABLE_DMA))
esp_dma_enable(ncr->devobject.lsistate, 1);
else if ((oldstate & FLSC_PB_ENABLE_DMA) && !(ncr->state & FLSC_PB_ENABLE_DMA))
esp_dma_enable(ncr->devobject.lsistate, 0);
set_irq2_fastlane(ncr);
} else if (addr == FASTLANE_RESETDMA) {
ncr->dma_cnt = 4;
ncr->dma_ptr = 0;
}
return;
} else if (addr < 0x01000000) {
addr &= 3;
addr = 3 - addr;
ncr->dma_ptr &= ~(0xff << (addr * 8));
ncr->dma_ptr |= (val & 0xff) << (addr * 8);
ncr->dma_cnt--;
if (ncr->dma_cnt == 0 && (ncr->state & FLSC_PB_ENABLE_DMA))
esp_dma_enable(ncr->devobject.lsistate, 1);
return;
}
} else if (currprefs.cpuboard_type == BOARD_BLIZZARD_2060) {
if (addr >= BLIZZARD_2060_DMA_OFFSET) {
//write_log (_T("Blizzard DMA PUT %08x %02X\n"), addr, (uae_u8)val);
addr &= 0xf;
addr >>= 2;
addr = 3 - addr;
ncr->dma_ptr &= ~(0xff << (addr * 8));
ncr->dma_ptr |= (val & 0xff) << (addr * 8);
if (addr == 3)
esp_dma_enable(ncr->devobject.lsistate, 1);
return;
} else if (addr >= BLIZZARD_2060_LED_OFFSET) {
