int main () { int i; /* Initialise handler vector */ int_init(); /* Install ethernet interrupt handler, it is enabled here too */ int_add(ETH0_IRQ, oeth_interrupt, 0); /* Enable interrupts in supervisor register */ cpu_enable_user_interrupts(); ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ /* clear tx_done, the tx interrupt handler will set it when it's been transmitted */ tx_done = 0; rx_done = 0; ethphy_set_100mbit(0); #ifndef ETH_TX_TEST_LENGTH # define ETH_TX_START_LENGTH 40 # define ETH_TX_TEST_LENGTH 1024 # define ETH_TX_TEST_LENGTH_INCREMENT 21 //# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE #endif for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH; i+=ETH_TX_TEST_LENGTH_INCREMENT) fill_and_tx_packet(i); ethphy_set_10mbit(0); for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH; i+=ETH_TX_TEST_LENGTH_INCREMENT) fill_and_tx_packet(i); exit(0x8000000d); }
int main () { /* Initialise handler vector */ int_init(); /* Install ethernet interrupt handler, it is enabled here too */ int_add(ETH0_IRQ, oeth_interrupt, 0); ethmac_setup(ETH0_PHY, ETH0_BUF); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ wprint("Entering loop\n"); while (1) { } ethmac_halt(); exit(0x8000000d); return 0; }
int main () { /* Initialise handler vector */ int_init(); /* Install ethernet interrupt handler, it is enabled here too */ int_add(ETH0_IRQ, oeth_interrupt, 0); ethmac_setup(ETH0_PHY, ETH0_BUF); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ /* clear tx_done, the tx interrupt handler will set it when it's been transmitted */ while (1) { char buf[120]; memcpy(buf, "Hello world!\n", 12); tx_packet(buf, sizeof(buf)); } exit(0x8000000d); }
int main () { tx_data_pointer = 0; /* Initialise handler vector */ int_init(); /* Install ethernet interrupt handler, it is enabled here too */ int_add(ETH0_IRQ, oeth_interrupt, 0); /* Enable interrupts in supervisor register */ cpu_enable_user_interrupts(); /* Enable CPU timer */ cpu_enable_timer(); ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ /* clear tx_done, the tx interrupt handler will set it when it's been transmitted */ tx_done = 0; rx_done = 0; ethphy_set_100mbit(0); send_ethmac_rxtx_test_init_packet(0x0); // 0x0 - call response test #define ETH_TX_MIN_PACKET_SIZE 512 #define ETH_TX_NUM_PACKETS 20 //int response_time = 150000; // Response time before response packet it sent // back (should be in nanoseconds). int response_time = 0; unsigned long num_to_check; for(num_to_check=ETH_TX_MIN_PACKET_SIZE; num_to_check<ETH_TX_MIN_PACKET_SIZE + ETH_TX_NUM_PACKETS; num_to_check++) fill_and_tx_call_packet(num_to_check, response_time); // Wait a moment for the RX packet check to complete before switching off RX for(num_to_check=0; num_to_check=1000; num_to_check++); oeth_disable_rx(); // Now for 10mbit mode... ethphy_set_10mbit(0); oeth_enable_rx(); for(num_to_check=ETH_TX_MIN_PACKET_SIZE; num_to_check<ETH_TX_MIN_PACKET_SIZE + ETH_TX_NUM_PACKETS; num_to_check++) fill_and_tx_call_packet(num_to_check, response_time); oeth_disable_rx(); // Go back to 100-mbit mode ethphy_set_100mbit(0); oeth_enable_rx(); for(num_to_check=ETH_TX_MIN_PACKET_SIZE; num_to_check<ETH_TX_NUM_PACKETS; num_to_check++) fill_and_tx_call_packet(num_to_check, response_time); exit(0x8000000d); }