static void etm_init_arch_data(void *info)
{
u32 etmidr;
u32 etmccr;
struct etm_drvdata *drvdata = info;
/* Make sure all registers are accessible */
etm_os_unlock(drvdata);
CS_UNLOCK(drvdata->base);
/* First dummy read */
(void)etm_readl(drvdata, ETMPDSR);
/* Provide power to ETM: ETMPDCR[3] == 1 */
etm_set_pwrup(drvdata);
/*
* Clear power down bit since when this bit is set writes to
* certain registers might be ignored.
*/
etm_clr_pwrdwn(drvdata);
/*
* Set prog bit. It will be set from reset but this is included to
* ensure it is set
*/
etm_set_prog(drvdata);
/* Find all capabilities */
etmidr = etm_readl(drvdata, ETMIDR);
drvdata->arch = BMVAL(etmidr, 4, 11);
drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
drvdata->etmccer = etm_readl(drvdata, ETMCCER);
etmccr = etm_readl(drvdata, ETMCCR);
drvdata->etmccr = etmccr;
drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
etm_set_pwrdwn(drvdata);
etm_clr_pwrup(drvdata);
CS_LOCK(drvdata->base);
}
static void etm_disable_perf(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
return;
CS_UNLOCK(drvdata->base);
/* Setting the prog bit disables tracing immediately */
etm_set_prog(drvdata);
/*
* There is no way to know when the tracer will be used again so
* power down the tracer.
*/
etm_set_pwrdwn(drvdata);
CS_LOCK(drvdata->base);
}
static void etm_disable_hw(void *info)
{
int i;
struct etm_drvdata *drvdata = info;
struct etm_config *config = &drvdata->config;
CS_UNLOCK(drvdata->base);
etm_set_prog(drvdata);
/* Read back sequencer and counters for post trace analysis */
config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
for (i = 0; i < drvdata->nr_cntr; i++)
config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
etm_set_pwrdwn(drvdata);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
}
static void etm_disable_hw(void *info)
{
int i;
struct etm_drvdata *drvdata = info;
CS_UNLOCK(drvdata->base);
etm_set_prog(drvdata);
/* Program trace enable to low by using always false event */
etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
/* Read back sequencer and counters for post trace analysis */
drvdata->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
for (i = 0; i < drvdata->nr_cntr; i++)
drvdata->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
etm_set_pwrdwn(drvdata);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
}
static void etm_enable_hw(void *info)
{
int i;
u32 etmcr;
struct etm_drvdata *drvdata = info;
CS_UNLOCK(drvdata->base);
/* Turn engine on */
etm_clr_pwrdwn(drvdata);
/* Apply power to trace registers */
etm_set_pwrup(drvdata);
/* Make sure all registers are accessible */
etm_os_unlock(drvdata);
etm_set_prog(drvdata);
etmcr = etm_readl(drvdata, ETMCR);
etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
etmcr |= drvdata->port_size;
etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1);
etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR);
for (i = 0; i < drvdata->nr_addr_cmp; i++) {
etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));
etm_writel(drvdata, drvdata->addr_acctype[i], ETMACTRn(i));
}
for (i = 0; i < drvdata->nr_cntr; i++) {
etm_writel(drvdata, drvdata->cntr_rld_val[i], ETMCNTRLDVRn(i));
etm_writel(drvdata, drvdata->cntr_event[i], ETMCNTENRn(i));
etm_writel(drvdata, drvdata->cntr_rld_event[i],
ETMCNTRLDEVRn(i));
etm_writel(drvdata, drvdata->cntr_val[i], ETMCNTVRn(i));
}
etm_writel(drvdata, drvdata->seq_12_event, ETMSQ12EVR);
etm_writel(drvdata, drvdata->seq_21_event, ETMSQ21EVR);
etm_writel(drvdata, drvdata->seq_23_event, ETMSQ23EVR);
etm_writel(drvdata, drvdata->seq_31_event, ETMSQ31EVR);
etm_writel(drvdata, drvdata->seq_32_event, ETMSQ32EVR);
etm_writel(drvdata, drvdata->seq_13_event, ETMSQ13EVR);
etm_writel(drvdata, drvdata->seq_curr_state, ETMSQR);
for (i = 0; i < drvdata->nr_ext_out; i++)
etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
etm_writel(drvdata, drvdata->ctxid_pid[i], ETMCIDCVRn(i));
etm_writel(drvdata, drvdata->ctxid_mask, ETMCIDCMR);
etm_writel(drvdata, drvdata->sync_freq, ETMSYNCFR);
/* No external input selected */
etm_writel(drvdata, 0x0, ETMEXTINSELR);
etm_writel(drvdata, drvdata->timestamp_event, ETMTSEVR);
/* No auxiliary control selected */
etm_writel(drvdata, 0x0, ETMAUXCR);
etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
/* No VMID comparator value selected */
etm_writel(drvdata, 0x0, ETMVMIDCVR);
/* Ensures trace output is enabled from this ETM */
etm_writel(drvdata, drvdata->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
etm_clr_prog(drvdata);
CS_LOCK(drvdata->base);
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
}
static int etm_enable_hw(struct etm_drvdata *drvdata)
{
int i, rc;
u32 etmcr;
struct etm_config *config = &drvdata->config;
CS_UNLOCK(drvdata->base);
rc = coresight_claim_device_unlocked(drvdata->base);
if (rc)
goto done;
/* Turn engine on */
etm_clr_pwrdwn(drvdata);
/* Apply power to trace registers */
etm_set_pwrup(drvdata);
/* Make sure all registers are accessible */
etm_os_unlock(drvdata);
etm_set_prog(drvdata);
etmcr = etm_readl(drvdata, ETMCR);
/* Clear setting from a previous run if need be */
etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
etmcr |= drvdata->port_size;
etmcr |= ETMCR_ETM_EN;
etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
etm_writel(drvdata, config->enable_event, ETMTEEVR);
etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
etm_writel(drvdata, config->fifofull_level, ETMFFLR);
for (i = 0; i < drvdata->nr_addr_cmp; i++) {
etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
}
for (i = 0; i < drvdata->nr_cntr; i++) {
etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
etm_writel(drvdata, config->cntr_rld_event[i],
ETMCNTRLDEVRn(i));
etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
}
etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
etm_writel(drvdata, config->seq_curr_state, ETMSQR);
for (i = 0; i < drvdata->nr_ext_out; i++)
etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
/* No external input selected */
etm_writel(drvdata, 0x0, ETMEXTINSELR);
etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
/* No auxiliary control selected */
etm_writel(drvdata, 0x0, ETMAUXCR);
etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
/* No VMID comparator value selected */
etm_writel(drvdata, 0x0, ETMVMIDCVR);
etm_clr_prog(drvdata);
done:
CS_LOCK(drvdata->base);
dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
drvdata->cpu, rc);
return rc;
}