int main(int argc, char **argv)
{
int rv;
int width, height;
int width_s, height_s;
int padded_width, padded_height;
int backbuffer = 0;
int supersample_x = 2; // 1 or 2
int supersample_y = 2; // 1 or 2
int extra_ps_inputs = 0;
fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
width_s = width * supersample_x;
height_s = height * supersample_y;
padded_width = etna_align_up(width_s, 64);
padded_height = etna_align_up(height_s, 64);
extra_ps_inputs = (supersample_x > 1 || supersample_y > 1); // in case of supersample, there is an extra input to PS
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
etna_vidmem *rt = 0; /* main render target */
etna_vidmem *rt_ts = 0; /* tile status for main render target */
etna_vidmem *z = 0; /* depth for main render target */
etna_vidmem *z_ts = 0; /* depth ts for main render target */
etna_vidmem *vtx = 0; /* vertex buffer */
etna_vidmem *idx = 0; /* index buffer */
etna_vidmem *aux_rt = 0; /* auxilary render target */
etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
etna_vidmem *tex = 0; /* texture */
etna_vidmem *bmp = 0; /* bitmap */
/* TODO: anti aliasing (doubles width/height) */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&idx, INDEX_BUFFER_SIZE, gcvSURF_INDEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&tex, 0x100000, gcvSURF_TEXTURE, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
memset(vtx->logical, 0, 0x5ef80);
#ifndef INDEXED
printf("Interleaving vertices...\n");
float *vertices_array = companion_vertices_array();
float *texture_coordinates_array =
companion_texture_coordinates_array();
float *normals_array = companion_normals_array();
assert(COMPANION_ARRAY_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_ARRAY_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vertices_array[vert*3 + comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = normals_array[vert*3 + comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = texture_coordinates_array[vert*2 + comp]; /* 2 */
}
#else
printf("Interleaving vertices and copying index buffer...\n");
assert(COMPANION_VERTEX_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE);
for(int vert=0; vert<COMPANION_VERTEX_COUNT; ++vert)
{
int dest_idx = vert * (3 + 3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = companion_vertices[vert][comp]; /* 0 */
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = companion_normals[vert][comp]; /* 1 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+6] = companion_texture_coordinates[vert][comp]; /* 2 */
}
assert(COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short) < INDEX_BUFFER_SIZE);
memcpy(idx->logical, &companion_triangles[0][0], COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short));
#endif
/* Fill in texture (convert from RGB linear to tiled) */
#define TILE_WIDTH (4)
#define TILE_HEIGHT (4)
#define TILE_WORDS (TILE_WIDTH*TILE_HEIGHT)
unsigned ytiles = COMPANION_TEXTURE_HEIGHT / TILE_HEIGHT;
unsigned xtiles = COMPANION_TEXTURE_WIDTH / TILE_WIDTH;
unsigned dst_stride = xtiles * TILE_WORDS;
for(unsigned ty=0; ty<ytiles; ++ty)
{
for(unsigned tx=0; tx<xtiles; ++tx)
{
unsigned ofs = ty * dst_stride + tx * TILE_WORDS;
for(unsigned y=0; y<TILE_HEIGHT; ++y)
{
for(unsigned x=0; x<TILE_WIDTH; ++x)
{
unsigned srcy = ty*TILE_HEIGHT + y;
unsigned srcx = tx*TILE_WIDTH + x;
unsigned src_ofs = (srcy*COMPANION_TEXTURE_WIDTH+srcx)*3;
unsigned r,g,b,a;
#ifndef TEST_PATTERN /* actual texture */
r = ((uint8_t*)companion_texture)[src_ofs+0];
g = ((uint8_t*)companion_texture)[src_ofs+1];
b = ((uint8_t*)companion_texture)[src_ofs+2];
#else /* test pattern */
r = srcx; g = srcy; b = 0;
#endif
a = 255;
((uint32_t*)tex->logical)[ofs] = ((a&0xFF) << 24) | ((b&0xFF) << 16) | ((g&0xFF) << 8) | (r&0xFF);
ofs += 1;
}
}
}
}
etna_ctx *ctx = 0;
if(etna_create(&ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
for(int frame=0; frame<1000; ++frame)
{
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) &
ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID) &
ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf) &
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, 1));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address);
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
uint32_t ts_msaa_config;
if(supersample_x == 2 && supersample_y == 2)
{
// 4X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(2), 0xaaa22a22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(8), 0x262a2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(9), 0x886688a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(10), 0x888866aa);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(11), 0x668888a6);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(1), 0xe6ae622a);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(4), 0x46622a88);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(5), 0x888888ae);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(6), 0x888888e6);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(7), 0x888888ca);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xeaa26e26);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x4a6e2688);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x888888a2);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x888888ea);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x888888c6);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else if(supersample_x == 2 && supersample_y == 1)
{
// 2X MSAA
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 2X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0);
etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xaa22);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x66aa2288);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x88558800);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x88881100);
etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x33888800);
ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8;
} else { // No multisampling
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
ts_msaa_config = 0;
}
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, 1) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1));
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address);
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address);
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
ts_msaa_config);
#ifdef EXTRA_DELAYS
/* Warm up RS on aux render target (is this needed?) */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical);
#endif
/* sync rasterizer to pixel engine after changes to PE config */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target and depth
* Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
/* clear color ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* clear depth ts */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, z_ts->address);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((z_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/** Done */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* depth setup */
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 1) &
ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_LESS) &
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly and setup engine */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* set up texture unit */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE);
etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0),
VIVS_TE_SAMPLER_SIZE_WIDTH(512)|VIVS_TE_SAMPLER_SIZE_HEIGHT(512));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0),
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(9<<5) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(9<<5));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,0), tex->address);
etna_set_state(ctx, VIVS_TE_SAMPLER_CONFIG0(0),
VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)|
VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)|
VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_NONE)|
VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)|
VIVS_TE_SAMPLER_CONFIG0_FORMAT(TEXTURE_FORMAT_X8R8G8B8));
etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0), 0x00000000); /* TE.SAMPLER[0].LOD_CONFIG := 0x0 */
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3),
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6),
/* VIVS_VS_OUTPUT(0) */ 0x10004});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
/* Now load the shader itself */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3);
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 1.0); /* u0.x */
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(1), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS,
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(4)| /* position */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(2) /* texture coordinate */
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP4(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP5(VARYING_COMPONENT_USE_USED)
, 0
});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT,
VIVS_PS_INPUT_COUNT_UNK8(31)| VIVS_PS_INPUT_COUNT_COUNT(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3 + extra_ps_inputs));
etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS,
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(6)); /* 4+2=6 total varying components */
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -9.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
esScale(&modelview, 0.475f, 0.475f, 0.475f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
ESMatrix projection;
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
ESMatrix modelviewprojection;
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
#ifdef INDEXED
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_BASE_ADDR, idx->address);
etna_set_state(ctx, VIVS_FE_INDEX_STREAM_CONTROL, VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT);
#endif
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address);
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE((3 + 3 + 2)*4));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_3 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x18));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_2 |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
#ifdef INDEXED
etna_draw_indexed_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT, 0);
#else
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
#endif
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
#ifdef EXTRA_DELAYS
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
#endif
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Wait for pixel engine to finish */
#ifdef EXTRA_DELAYS
etna_finish(ctx);
#else
etna_stall(ctx, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
#endif
/* Copy result to framebuffer */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
((supersample_x>1)?VIVS_RS_CONFIG_DOWNSAMPLE_X:0) |
((supersample_y>1)?VIVS_RS_CONFIG_DOWNSAMPLE_Y:0) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height * supersample_y) |
VIVS_RS_WINDOW_SIZE_WIDTH(width * supersample_x));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
etna_free(ctx);
viv_close();
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width = etna_align_up(width, 8);
int padded_height = etna_align_up(height, 1);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_2D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
struct etna_vidmem *bmp = 0; /* bitmap */
struct etna_vidmem *src = 0; /* source */
size_t bmp_size = width * height * 4;
size_t src_size = width * height * 4;
if(etna_vidmem_alloc_linear(conn, &bmp, bmp_size, VIV_SURF_BITMAP, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &src, src_size, VIV_SURF_BITMAP, VIV_POOL_DEFAULT, true)!=ETNA_OK)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* switch to 2D pipe */
etna_set_pipe(ctx, ETNA_PIPE_2D);
/* pre-clear surface. Could use the 2D engine for this,
* but we're lazy.
*/
for(int i=0; i<bmp_size/4; ++i)
((uint32_t*)bmp->logical)[i] = 0xff000000;
/* Make pattern */
for(int y=0; y<8; ++y)
{
for(int x=0; x<8; ++x)
{
uint8_t a = 0xff;
uint8_t r = x*32;
uint8_t g = y*32;
uint8_t b = 0x12;
((uint32_t*)src->logical)[y*8+x] = ((uint32_t)a << 24)|((uint32_t)b<<16)|((uint32_t)g<<8)|(uint32_t)r;
}
}
for(int frame=0; frame<1; ++frame)
{
printf("*** FRAME %i ****\n", frame);
etna_set_state(ctx, VIVS_DE_SRC_ADDRESS, 0);
etna_set_state(ctx, VIVS_DE_SRC_STRIDE, width*4);
etna_set_state(ctx, VIVS_DE_SRC_ROTATION_CONFIG, 0);
etna_set_state(ctx, VIVS_DE_SRC_CONFIG,
VIVS_DE_SRC_CONFIG_UNK16 |
VIVS_DE_SRC_CONFIG_SOURCE_FORMAT(DE_FORMAT_MONOCHROME) |
VIVS_DE_SRC_CONFIG_LOCATION_MEMORY |
VIVS_DE_SRC_CONFIG_PACK_PACKED8 |
VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT(DE_FORMAT_MONOCHROME));
etna_set_state(ctx, VIVS_DE_SRC_ORIGIN, 0);
etna_set_state(ctx, VIVS_DE_SRC_SIZE, 0);
etna_set_state(ctx, VIVS_DE_SRC_COLOR_BG, 0xff44ff44);
etna_set_state(ctx, VIVS_DE_SRC_COLOR_FG, 0xff44ff44);
etna_set_state(ctx, VIVS_DE_STRETCH_FACTOR_LOW, 0);
etna_set_state(ctx, VIVS_DE_STRETCH_FACTOR_HIGH, 0);
etna_set_state(ctx, VIVS_DE_DEST_ADDRESS, bmp->address);
etna_set_state(ctx, VIVS_DE_DEST_STRIDE, width*4);
etna_set_state(ctx, VIVS_DE_DEST_ROTATION_CONFIG, 0);
etna_set_state(ctx, VIVS_DE_DEST_CONFIG,
VIVS_DE_DEST_CONFIG_FORMAT(DE_FORMAT_A8R8G8B8) |
VIVS_DE_DEST_CONFIG_COMMAND_LINE |
VIVS_DE_DEST_CONFIG_SWIZZLE(DE_SWIZZLE_ARGB) |
VIVS_DE_DEST_CONFIG_TILED_DISABLE |
VIVS_DE_DEST_CONFIG_MINOR_TILED_DISABLE
);
etna_set_state(ctx, VIVS_DE_ROP,
VIVS_DE_ROP_ROP_FG(0xf0) | VIVS_DE_ROP_ROP_BG(0xf0) | VIVS_DE_ROP_TYPE_ROP4);
etna_set_state(ctx, VIVS_DE_CLIP_TOP_LEFT,
VIVS_DE_CLIP_TOP_LEFT_X(0) |
VIVS_DE_CLIP_TOP_LEFT_Y(0)
);
etna_set_state(ctx, VIVS_DE_CLIP_BOTTOM_RIGHT,
VIVS_DE_CLIP_BOTTOM_RIGHT_X(width) |
VIVS_DE_CLIP_BOTTOM_RIGHT_Y(height)
);
etna_set_state(ctx, VIVS_DE_CONFIG, 0); /* TODO */
etna_set_state(ctx, VIVS_DE_SRC_ORIGIN_FRACTION, 0);
etna_set_state(ctx, VIVS_DE_ALPHA_CONTROL, 0);
etna_set_state(ctx, VIVS_DE_ALPHA_MODES, 0);
etna_set_state(ctx, VIVS_DE_DEST_ROTATION_HEIGHT, 0);
etna_set_state(ctx, VIVS_DE_SRC_ROTATION_HEIGHT, 0);
etna_set_state(ctx, VIVS_DE_ROT_ANGLE, 0);
etna_set_state(ctx, VIVS_DE_PATTERN_ADDRESS, src->address);
etna_set_state(ctx, VIVS_DE_PATTERN_CONFIG,
VIVS_DE_PATTERN_CONFIG_FORMAT(DE_FORMAT_A8R8G8B8) |
VIVS_DE_PATTERN_CONFIG_TYPE_PATTERN);
etna_set_state(ctx, VIVS_DE_PATTERN_MASK_LOW, 0xffffffff);
etna_set_state(ctx, VIVS_DE_PATTERN_MASK_HIGH, 0xffffffff);
etna_set_state(ctx, VIVS_DE_DEST_COLOR_KEY, 0);
etna_set_state(ctx, VIVS_DE_GLOBAL_SRC_COLOR, 0);
etna_set_state(ctx, VIVS_DE_GLOBAL_DEST_COLOR, 0);
etna_set_state(ctx, VIVS_DE_COLOR_MULTIPLY_MODES, 0);
etna_set_state(ctx, VIVS_DE_PE_TRANSPARENCY, 0);
etna_set_state(ctx, VIVS_DE_PE_CONTROL, 0);
etna_set_state(ctx, VIVS_DE_PE_DITHER_LOW, 0xffffffff);
etna_set_state(ctx, VIVS_DE_PE_DITHER_HIGH, 0xffffffff);
#define NUM_RECTS (2)
/* Queue DE command */
etna_reserve(ctx, 256*2 + 2);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D |
VIV_FE_DRAW_2D_HEADER_COUNT(NUM_RECTS);
(ctx)->offset++; /* rectangles start aligned */
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_TOP_LEFT_X(0) |
VIV_FE_DRAW_2D_TOP_LEFT_Y(0);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(width) |
VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(height);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_TOP_LEFT_X(width) |
VIV_FE_DRAW_2D_TOP_LEFT_Y(0);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(0) |
VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(height);
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_PE2D);
etna_finish(ctx);
}
bmp_dump32(bmp->logical, width, height, false, "/tmp/fb.bmp");
printf("Dump complete\n");
/* Unlock video memory */
if(etna_vidmem_unlock(conn, bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close(conn);
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width = etna_align_up(width, 64);
int padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_3D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
struct etna_vidmem *rt = 0; /* main render target */
struct etna_vidmem *rt_ts = 0; /* tile status for main render target */
struct etna_vidmem *z = 0; /* depth for main render target */
struct etna_vidmem *z_ts = 0; /* depth ts for main render target */
struct etna_vidmem *vtx = 0; /* vertex buffer */
struct etna_vidmem *aux_rt = 0; /* auxilary render target */
struct etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
struct etna_vidmem *bmp = 0; /* bitmap */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(conn, &rt, rt_size, VIV_SURF_RENDER_TARGET, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &rt_ts, rt_ts_size, VIV_SURF_TILE_STATUS, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z, z_size, VIV_SURF_DEPTH, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z_ts, z_ts_size, VIV_SURF_TILE_STATUS, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &vtx, VERTEX_BUFFER_SIZE, VIV_SURF_VERTEX, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt, 0x4000, VIV_SURF_RENDER_TARGET, VIV_POOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt_ts, 0x100, VIV_SURF_TILE_STATUS, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &bmp, bmp_size, VIV_SURF_BITMAP, VIV_POOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int dest_idx = vert * (3 + 2);
for(int comp=0; comp<3; ++comp)
((float*)vtx->logical)[dest_idx+comp+0] = vVertices[vert*3 + comp]; /* 0 */
for(int comp=0; comp<2; ++comp)
((float*)vtx->logical)[dest_idx+comp+3] = vTexCoords[vert*2 + comp]; /* 1 */
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* Now load the shader itself */
uint32_t vs[] = {
0x02001001, 0x2a800800, 0x00000000, 0x003fc008,
0x02001003, 0x2a800800, 0x00000040, 0x00000002,
};
uint32_t vs_size = sizeof(vs);
uint32_t *ps;
uint32_t ps_size;
if(argc < 2)
{
perror("provide shader on command line");
exit(1);
}
int fd = open(argv[1], O_RDONLY);
if(fd == -1)
{
perror("opening shader");
exit(1);
}
ps_size = lseek(fd, 0, SEEK_END);
ps = malloc(ps_size);
lseek(fd, 0, SEEK_SET);
if(ps_size == 0 || ps_size>8192 || read(fd, ps, ps_size) != ps_size)
{
perror("empty or unreadable shader");
exit(1);
}
close(fd);
/* XXX how important is the ordering? I suppose we could group states (except the flushes, kickers, semaphores etc)
* and simply submit them at once. Especially for consecutive states and masked stated this could be a big win
* in DMA command buffer size. */
/* Build first command buffer */
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Set up pixel engine */
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, OFF));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
/* Set up render target */
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_A8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, 1));
for(int frame=0; frame<1; ++frame)
{
printf("*** FRAME %i ****\n", frame);
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 1));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, 1)
);
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); /* flip-flopping once again */
/* Warm up RS on aux render target */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
/* Phew, now that's one hell of a setup; the serious rendering starts now */
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
/* ... or so we thought */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
/* maybe now? */
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* nope, not really... */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target
* What the blob does is regard the TS as an image of width N, height 4, with 4 bytes per pixel
* Looks like the height always stays the same. I don't think it matters as long as the entire memory are is covered.
* XXX need to clear the depth ts too.
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x100); /* 0x100 iso 0x40! seems it uses a width of 256 if width divisible by 256, XXX need to figure out these rules */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(rt_ts_size/0x100) |
VIVS_RS_WINDOW_SIZE_WIDTH(64));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
//etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, NONE));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_ALWAYS));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
/* VIVS_VS_INPUT_COUNT */ (1<<8) | 2,
/* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(2),
/* VIVS_VS_OUTPUT(0) */ 0x100});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(0), 0.5); /* u0.x */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x3); /* huh, this is 1 for the cubes */
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, /* one varying, with two components */
VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(2)
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){ /* one varying, with four components */
VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_UNUSED) |
VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_UNUSED)
, 0
});
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 0.0); /* u0.x */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(1), 1.0); /* u0.y */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(2), 0.5); /* u0.z */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(3), 2.0); /* u0.w */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(4), 1/256.0); /* u1.x */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(5), 16.0); /* u1.y */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(6), 10.0); /* u1.z */
etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(8), frame); /* u2.x */
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT, (31<<8)|2);
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(4));
etna_set_state(ctx, VIVS_PS_CONTROL,
VIVS_PS_CONTROL_UNK1
);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x100);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, /* one varying, with two components, must be
changed together with GL_VARYING_NUM_COMPONENTS */
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(2)
);
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0582);
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 2);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(0x14));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(2) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x14));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x00100); /* 0x20000 in etna_cube */
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, 0, 2);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* Submit first command buffer */
etna_flush(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | VIVS_RS_DEST_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* Submit second command buffer */
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0));
/* Submit third command buffer, wait for pixel engine to finish */
etna_finish(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) /*|
VIVS_RS_CONFIG_SWAP_RB*/);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | VIVS_RS_SOURCE_STRIDE_TILING);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, width * 4);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, bmp->address); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
}
if(argc>2)
{
printf("Dumping image to %s\n", argv[2]);
bmp_dump32(bmp->logical, width, height, true, argv[2]);
}
/* Unlock video memory */
if(etna_vidmem_unlock(conn, bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close(conn);
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width, padded_height;
int backbuffer = 0;
struct fb_info fb;
rv = fb_open(0, &fb);
if(rv!=0)
{
exit(1);
}
width = fb.fb_var.xres;
height = fb.fb_var.yres;
padded_width = etna_align_up(width, 64);
padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_3D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
struct etna_vidmem *rt = 0; /* main render target */
struct etna_vidmem *rt_ts = 0; /* tile status for main render target */
struct etna_vidmem *z = 0; /* depth for main render target */
struct etna_vidmem *z_ts = 0; /* depth ts for main render target */
struct etna_vidmem *aux_rt = 0; /* auxilary render target */
struct etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)/0x100, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
if(etna_vidmem_alloc_linear(conn, &rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &aux_rt_ts, 0x100, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
memset(rt_ts->logical, 0x55, rt_ts->size); // Pattern: cleared
//memset(rt_ts->logical, 0xAA, rt_ts->size); // Pattern: weird pattern fill
//memset(rt_ts->logical, 0x00, rt_ts->size); // Pattern: filled in (nothing to do)
//memset(rt_ts->logical, 0xFF, rt_ts->size); // Pattern: weird pattern fill
uint32_t pixelfmt = RS_FORMAT_X8R8G8B8;
bool supertiled = true;
bool tiled = true;
uint32_t stride = 0;
if(tiled)
{
stride = (padded_width * 4 * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0);
} else {
stride = (padded_width * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0);
}
for(int frame=0; frame<1; ++frame)
{
if(frame%50 == 0)
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
/* Does this affect the RS? It appears not. */
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
/* Set up resolve to self */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
#if 0 /* don't care about depth, for now */
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
#endif
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
/*VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION*/);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_SOURCE_TILED:0) |
VIVS_RS_CONFIG_DEST_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_DEST_TILED:0));
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_set_state(ctx, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH | VIVS_GL_FLUSH_CACHE_COLOR);
/* Clear part using normal (not fast) clear */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff});
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(0x100) |
VIVS_RS_WINDOW_SIZE_WIDTH(0x100));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), 0xffff0000);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(1), 0xff00ff00);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(2), 0xff0000ff);
etna_set_state(ctx, VIVS_RS_FILL_VALUE(3), 0xffff00ff);
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, 0); /* fill disregards source anyway */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address + 64*64*4); /* Offset one entire 64*64 tile. Interesting things happen if only a partial tile is offset. */
/* Pure FILL_VALUE(0) */
//etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
/* Vertical line pattern */
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
/* Same as ENABLED2 */
//etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2 | VIVS_RS_CLEAR_CONTROL_BITS(0xffff));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
etna_finish(ctx);
#if 0
/* manually fill, to figure out tiling pattern */
for(int x=0; x<16384/4; ++x)
{
int a = (x & 0x3F) << 2;
int b = ((x >> 3) & 0x3F) << 2;
int c = ((x >> 6) & 0x3F) << 2;
((uint32_t*)(rt->logical + 16384*6))[x] = (a & 0xFF) | ((b & 0xFF) << 8) | ((c & 0xFF) << 16);
printf("%08x\n", (a & 0xFF) | ((b & 0xFF) << 8) | ((c & 0xFF) << 16));
}
#endif
/* Copy image to screen */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(pixelfmt) |
(tiled?VIVS_RS_CONFIG_SOURCE_TILED:0) |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SWAP_RB);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, stride);
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fb.fb_fix.line_length);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, fb.physical[backbuffer]); /* ADDR_J */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
/* switch buffers */
fb_set_buffer(&fb, backbuffer);
backbuffer = 1-backbuffer;
}
#ifdef DUMP
bmp_dump32(fb.logical[1-backbuffer], width, height, false, "/mnt/sdcard/fb.bmp");
printf("Dump complete\n");
#endif
etna_free(ctx);
viv_close(conn);
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
int padded_width = etna_align_up(width, 64);
int padded_height = etna_align_up(height, 64);
printf("padded_width %i padded_height %i\n", padded_width, padded_height);
rv = viv_open();
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
bool supertiled = VIV_FEATURE(chipMinorFeatures0,SUPER_TILED);
unsigned bits_per_tile = VIV_FEATURE(chipMinorFeatures0,2BITPERTILE)?2:4;
printf("Supertile: %i, bits per tile: %i\n", supertiled, bits_per_tile);
etna_vidmem *rt = 0; /* main render target */
etna_vidmem *rt_ts = 0; /* tile status for main render target */
etna_vidmem *z = 0; /* depth for main render target */
etna_vidmem *z_ts = 0; /* depth ts for main render target */
etna_vidmem *vtx = 0; /* vertex buffer */
etna_vidmem *aux_rt = 0; /* auxilary render target */
etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */
etna_vidmem *bmp = 0; /* bitmap */
size_t rt_size = padded_width * padded_height * 4;
size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)*bits_per_tile/0x80, 0x100);
size_t z_size = padded_width * padded_height * 2;
size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)*bits_per_tile/0x80, 0x100);
size_t bmp_size = width * height * 4;
if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&aux_rt_ts, 0x80*bits_per_tile, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(&bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK
)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
/* Phew, now we got all the memory we need.
* Write interleaved attribute vertex stream.
* Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished
* from GL by using a vertex buffer object.
*/
for(int vert=0; vert<NUM_VERTICES; ++vert)
{
int src_idx = vert * COMPONENTS_PER_VERTEX;
int dest_idx = vert * COMPONENTS_PER_VERTEX * 3;
for(int comp=0; comp<COMPONENTS_PER_VERTEX; ++comp)
{
((float*)vtx->logical)[dest_idx+comp+0] = vVertices[src_idx + comp]; /* 0 */
((float*)vtx->logical)[dest_idx+comp+3] = vNormals[src_idx + comp]; /* 1 */
((float*)vtx->logical)[dest_idx+comp+6] = vColors[src_idx + comp]; /* 2 */
}
}
etna_ctx *ctx = 0;
if(etna_create(&ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* XXX how important is the ordering? I suppose we could group states (except the flushes, kickers, semaphores etc)
* and simply submit them at once. Especially for consecutive states and masked stated this could be a big win
* in DMA command buffer size. */
for(int frame=0; frame<1; ++frame)
{
printf("*** FRAME %i ****\n", frame);
/* XXX part of this can be put outside the loop, but until we have usable context management
* this is safest.
*/
etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0));
etna_set_state(ctx, VIVS_SE_CONFIG, 0x0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG,
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) &
ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) &
ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD));
etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR,
VIVS_PE_ALPHA_BLEND_COLOR_B(0) |
VIVS_PE_ALPHA_BLEND_COLOR_G(0) |
VIVS_PE_ALPHA_BLEND_COLOR_R(0) |
VIVS_PE_ALPHA_BLEND_COLOR_A(0));
etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, OFF));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) &
ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) &
ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED));
etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) &
ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0);
etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID));
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH));
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) &
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, supertiled));
etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4);
etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG,
ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) &
ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0)
);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 1));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG,
ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) &
ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, supertiled)
);
etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2);
etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff);
etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */
etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); /* flip-flopping once again */
/* Warm up RS on aux render target */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up the resolve to clear tile status for main render target
* Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row)
* XXX need to clear the depth ts too.
* */
etna_set_state(ctx, VIVS_RS_CONFIG,
(RS_FORMAT_X8R8G8B8 << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) |
(RS_FORMAT_X8R8G8B8 << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT)
);
etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]) {
0xffffffff, 0xffffffff
});
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) |
(16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT));
etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), (bits_per_tile==4)?0x11111111:0x55555555);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL,
VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 |
(0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT));
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG,
0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_KICKER,
0xbeebbeeb);
/** Done */
etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW));
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, NONE));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_ALWAYS));
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z));
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0);
etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0);
/* set up primitive assembly */
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0);
etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0);
etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0));
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15);
etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5);
etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5);
/* shader setup */
etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16);
etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]) {
/* VIVS_VS_INPUT_COUNT */ (1<<8) | 3,
/* VIVS_VS_TEMP_REGISTER_CONTROL */ 6 << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT,
/* VIVS_VS_OUTPUT(0) */ 4
});
etna_set_state(ctx, VIVS_VS_START_PC, 0x0);
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */
etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */
/* Now load the shader itself */
etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
etna_set_state(ctx, VIVS_RA_CONTROL, 0x1);
etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]) {
/* VIVS_PS_END_PC */ ps_size/16,
/* VIVS_PS_OUTPUT_REG */ 0x1
});
etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200);
etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, /* one varying, with four components */
(4 << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT)
);
etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]) { /* one varying, with four components */
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) |
(VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT)
, 0
});
etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
etna_set_state(ctx, VIVS_PS_INPUT_COUNT, (31<<8)|2);
etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL,
(2 << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT));
etna_set_state(ctx, VIVS_PS_CONTROL,
VIVS_PS_CONTROL_UNK1
);
etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x100);
etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, /* one varying, with four components */
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(4)
);
etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0582);
etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 2);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0));
/* Compute transform matrices in the same way as cube egl demo */
ESMatrix modelview;
esMatrixLoadIdentity(&modelview);
esTranslate(&modelview, 0.0f, 0.0f, -8.0f);
esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f);
esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f);
esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f);
GLfloat aspect = (GLfloat)(height) / (GLfloat)(width);
ESMatrix projection;
esMatrixLoadIdentity(&projection);
esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f);
ESMatrix modelviewprojection;
esMatrixLoadIdentity(&modelviewprojection);
esMatrixMultiply(&modelviewprojection, &modelview, &projection);
ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */
esMatrixInverse3x3(&inverse, &modelview);
esMatrixTranspose(&normal, &inverse);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]);
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */
etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]);
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */
etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL,
0x24 << VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT);
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0x0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2),
VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT |
(ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE |
(0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) |
(3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) |
VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
(0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) |
(0x24 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT));
etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
for(int prim=0; prim<6; ++prim)
{
etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, prim*4, 2);
}
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_flush(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_DEST_TILED);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) |
VIVS_RS_WINDOW_SIZE_WIDTH(padded_width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
/* Submit second command buffer */
etna_flush(ctx);
etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address);
etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */
etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR |
VIVS_TS_MEM_CONFIG_DEPTH_16BPP |
VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
etna_set_state(ctx, VIVS_PE_COLOR_FORMAT,
ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0));
/* Submit third command buffer, wait for pixel engine to finish */
etna_finish(ctx);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_set_state(ctx, VIVS_RS_CONFIG,
VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) |
VIVS_RS_CONFIG_SOURCE_TILED |
VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) /*|
VIVS_RS_CONFIG_SWAP_RB*/);
etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0));
etna_set_state(ctx, VIVS_RS_DEST_STRIDE, width * 4);
etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff);
etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff);
etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED);
etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */
etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address);
etna_set_state(ctx, VIVS_RS_DEST_ADDR, bmp->address);
etna_set_state(ctx, VIVS_RS_WINDOW_SIZE,
VIVS_RS_WINDOW_SIZE_HEIGHT(height) |
VIVS_RS_WINDOW_SIZE_WIDTH(width));
etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb);
etna_finish(ctx);
}
bmp_dump32(bmp->logical, width, height, false, "/tmp/fb.bmp");
printf("Dump complete\n");
/* Unlock video memory */
if(etna_vidmem_unlock(bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close();
return 0;
}
int main(int argc, char **argv)
{
int rv;
int width = 256;
int height = 256;
size_t dst_stride = etna_align_up(width, 8) * 4;
struct viv_conn *conn = 0;
rv = viv_open(VIV_HW_2D, &conn);
if(rv!=0)
{
fprintf(stderr, "Error opening device\n");
exit(1);
}
printf("Succesfully opened device\n");
/* Read test image */
int src_width, src_height, src_stride;
uint32_t *src_data = 0;
if(!read_png("amethyst256.png", 8*4, &src_stride, &src_width, &src_height, &src_data))
{
printf("Unable to read amethyst256.png in current directory\n");
exit(1);
}
struct etna_vidmem *bmp = 0; /* bitmap */
struct etna_vidmem *src = 0; /* source */
size_t bmp_size = dst_stride * height;
size_t src_size = src_stride * src_height;
if(etna_vidmem_alloc_linear(conn, &bmp, bmp_size, VIV_SURF_BITMAP, VIV_POOL_DEFAULT, true)!=ETNA_OK ||
etna_vidmem_alloc_linear(conn, &src, src_size, VIV_SURF_BITMAP, VIV_POOL_DEFAULT, true)!=ETNA_OK)
{
fprintf(stderr, "Error allocating video memory\n");
exit(1);
}
struct etna_ctx *ctx = 0;
if(etna_create(conn, &ctx) != ETNA_OK)
{
printf("Unable to create context\n");
exit(1);
}
/* switch to 2D pipe */
etna_set_pipe(ctx, ETNA_PIPE_2D);
/* pre-clear surface. Could use the 2D engine for this,
* but we're lazy.
*/
for(int i=0; i<bmp_size/4; ++i)
((uint32_t*)bmp->logical)[i] = 0xff000000;
memcpy(src->logical, src_data, src_height * src_stride);
for(int frame=0; frame<1; ++frame)
{
printf("*** FRAME %i ****\n", frame);
etna_set_state(ctx, VIVS_DE_SRC_ADDRESS, src->address);
etna_set_state(ctx, VIVS_DE_SRC_STRIDE, src_stride);
etna_set_state(ctx, VIVS_DE_SRC_ROTATION_CONFIG,
VIVS_DE_SRC_ROTATION_CONFIG_WIDTH(src_width) |
VIVS_DE_SRC_ROTATION_CONFIG_ROTATION_ENABLE);
etna_set_state(ctx, VIVS_DE_SRC_ROTATION_HEIGHT,
VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT(src_height));
etna_set_state(ctx, VIVS_DE_SRC_CONFIG,
VIVS_DE_SRC_CONFIG_SOURCE_FORMAT(DE_FORMAT_A8R8G8B8) |
VIVS_DE_SRC_CONFIG_LOCATION_MEMORY |
VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT(DE_FORMAT_A8R8G8B8));
etna_set_state(ctx, VIVS_DE_SRC_ORIGIN,
VIVS_DE_SRC_ORIGIN_X(28) |
VIVS_DE_SRC_ORIGIN_Y(28));
etna_set_state(ctx, VIVS_DE_SRC_SIZE,
VIVS_DE_SRC_SIZE_X(width) |
VIVS_DE_SRC_SIZE_Y(height)
); // source size is ignored
etna_set_state(ctx, VIVS_DE_SRC_COLOR_BG, 0xff303030);
etna_set_state(ctx, VIVS_DE_SRC_COLOR_FG, 0xff12ff56);
etna_set_state(ctx, VIVS_DE_STRETCH_FACTOR_LOW, 0);
etna_set_state(ctx, VIVS_DE_STRETCH_FACTOR_HIGH, 0);
etna_set_state(ctx, VIVS_DE_DEST_ADDRESS, bmp->address);
etna_set_state(ctx, VIVS_DE_DEST_STRIDE, dst_stride);
etna_set_state(ctx, VIVS_DE_DEST_ROTATION_CONFIG,
VIVS_DE_DEST_ROTATION_CONFIG_WIDTH(width) |
VIVS_DE_DEST_ROTATION_CONFIG_ROTATION_DISABLE);
etna_set_state(ctx, VIVS_DE_DEST_ROTATION_HEIGHT,
VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT(height));
etna_set_state(ctx, VIVS_DE_DEST_CONFIG,
VIVS_DE_DEST_CONFIG_FORMAT(DE_FORMAT_A8R8G8B8) |
VIVS_DE_DEST_CONFIG_COMMAND_BIT_BLT |
VIVS_DE_DEST_CONFIG_SWIZZLE(DE_SWIZZLE_ARGB) |
VIVS_DE_DEST_CONFIG_TILED_DISABLE |
VIVS_DE_DEST_CONFIG_MINOR_TILED_DISABLE
);
etna_set_state(ctx, VIVS_DE_ROP,
VIVS_DE_ROP_ROP_FG(0xcc) | VIVS_DE_ROP_ROP_BG(0xcc) | VIVS_DE_ROP_TYPE_ROP4);
etna_set_state(ctx, VIVS_DE_CLIP_TOP_LEFT,
VIVS_DE_CLIP_TOP_LEFT_X(0) |
VIVS_DE_CLIP_TOP_LEFT_Y(0)
);
etna_set_state(ctx, VIVS_DE_CLIP_BOTTOM_RIGHT,
VIVS_DE_CLIP_BOTTOM_RIGHT_X(width) |
VIVS_DE_CLIP_BOTTOM_RIGHT_Y(height)
);
etna_set_state(ctx, VIVS_DE_CONFIG,
VIVS_DE_CONFIG_MIRROR_BLT_ENABLE_OFF |
VIVS_DE_CONFIG_MIRROR_BLT_MODE_NORMAL
);
etna_set_state(ctx, VIVS_DE_SRC_ORIGIN_FRACTION, 0);
etna_set_state(ctx, VIVS_DE_ALPHA_CONTROL, 0);
etna_set_state(ctx, VIVS_DE_ALPHA_MODES, 0);
etna_set_state(ctx, VIVS_DE_ROT_ANGLE, 0);
/* Clear color PE20 */
etna_set_state(ctx, VIVS_DE_CLEAR_PIXEL_VALUE32, 0xff40ff40);
/* Clear color PE10 */
etna_set_state(ctx, VIVS_DE_CLEAR_BYTE_MASK, 0xff);
etna_set_state(ctx, VIVS_DE_CLEAR_PIXEL_VALUE_LOW, 0xff40ff40);
etna_set_state(ctx, VIVS_DE_CLEAR_PIXEL_VALUE_HIGH, 0xff40ff40);
etna_set_state(ctx, VIVS_DE_DEST_COLOR_KEY, 0);
etna_set_state(ctx, VIVS_DE_GLOBAL_SRC_COLOR, 0);
etna_set_state(ctx, VIVS_DE_GLOBAL_DEST_COLOR, 0);
etna_set_state(ctx, VIVS_DE_COLOR_MULTIPLY_MODES, 0);
etna_set_state(ctx, VIVS_DE_PE_TRANSPARENCY, 0);
etna_set_state(ctx, VIVS_DE_PE_CONTROL, 0);
etna_set_state(ctx, VIVS_DE_PE_DITHER_LOW, 0xffffffff);
etna_set_state(ctx, VIVS_DE_PE_DITHER_HIGH, 0xffffffff);
#define NUM_RECTS (1)
/* Queue DE command */
etna_reserve(ctx, 256*2 + 2);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D |
VIV_FE_DRAW_2D_HEADER_COUNT(NUM_RECTS) |
VIV_FE_DRAW_2D_HEADER_DATA_COUNT(0);
(ctx)->offset++; /* rectangles start aligned */
for(int rec=0; rec<NUM_RECTS; ++rec)
{
int tgt_width = 200;
int tgt_height = 200;
int x1 = 28;
int y1 = 28;
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_TOP_LEFT_X(x1) |
VIV_FE_DRAW_2D_TOP_LEFT_Y(y1);
(ctx)->buf[(ctx)->offset++] = VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x1 + tgt_width) |
VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(y1 + tgt_height);
}
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, 1, 0);
etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_PE2D);
etna_finish(ctx);
}
bmp_dump32_noflip(bmp->logical, width, height, true, "/tmp/fb.bmp");
printf("Dump complete\n");
/* Unlock video memory */
if(etna_vidmem_unlock(conn, NULL, bmp) != 0)
{
fprintf(stderr, "Cannot unlock vidmem\n");
exit(1);
}
etna_free(ctx);
viv_close(conn);
return 0;
}
static void *etna_pipe_transfer_map(struct pipe_context *pipe,
struct pipe_resource *resource,
unsigned level,
unsigned usage, /* a combination of PIPE_TRANSFER_x */
const struct pipe_box *box,
struct pipe_transfer **out_transfer)
{
struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct etna_transfer *ptrans = util_slab_alloc(&priv->transfer_pool);
struct etna_resource *resource_priv = etna_resource(resource);
enum pipe_format format = resource->format;
if (!ptrans)
return NULL;
assert(level <= resource->last_level);
/* PIPE_TRANSFER_READ always requires a sync. */
if(usage & PIPE_TRANSFER_READ)
{
etna_finish(priv->ctx);
}
/* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be ignored when mapping in-place,
* but when not in place we need to fire off the copy operation in transfer_flush_region (currently
* a no-op) instead of unmap. Need to handle this to support ARB_map_buffer_range extension at least.
*/
/* XXX we don't take care of current operations on the resource; which can be, at some point in the pipeline
which is not yet executed:
- bound as surface
- bound through vertex buffer
- bound through index buffer
- bound in sampler view
- used in clear_render_target / clear_depth_stencil operation
- used in blit
- used in resource_copy_region
How do other drivers record this information over course of the rendering pipeline?
Is it necessary at all? Only in case we want to provide a fast path and map the resource directly
(and for PIPE_TRANSFER_MAP_DIRECTLY) and we don't want to force a sync.
We also need to know whether the resource is in use to determine if a sync is needed (or just do it
always, but that comes at the expense of performance).
A conservative approximation without too much overhead would be to mark all resources that have
been bound at some point as busy. A drawback would be that accessing resources that have
been bound but are no longer in use for a while still carry a performance penalty. On the other hand,
the program could be using PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE or PIPE_TRANSFER_UNSYNCHRONIZED to
avoid this in the first place...
A) We use an in-pipe copy engine, and queue the copy operation after unmap so that the copy
will be performed when all current commands have been executed.
Using the RS is possible, not sure if always efficient. This can also do any kind of tiling for us.
Only possible when PIPE_TRANSFER_DISCARD_RANGE is set.
B) We discard the entire resource (or at least, the mipmap level) and allocate new memory for it.
Only possible when mapping the entire resource or PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set.
*/
/* No need to allocate a buffer for copying if the resource is not in use,
* and no tiling is needed, can just return a direct pointer.
*/
ptrans->in_place = resource_priv->layout == ETNA_LAYOUT_LINEAR ||
(resource_priv->layout == ETNA_LAYOUT_TILED && util_format_is_compressed(resource->format));
ptrans->base.resource = resource;
ptrans->base.level = level;
ptrans->base.usage = usage;
ptrans->base.box = *box;
struct etna_resource_level *res_level = &resource_priv->levels[level];
/* map buffer object */
void *mapped = etna_bo_map(resource_priv->bo) + res_level->offset;
if(likely(ptrans->in_place))
{
ptrans->base.stride = res_level->stride;
ptrans->base.layer_stride = res_level->layer_stride;
ptrans->buffer = mapped + etna_compute_offset(resource->format, box, res_level->stride, res_level->layer_stride);
} else {
unsigned divSizeX = util_format_get_blockwidth(format);
unsigned divSizeY = util_format_get_blockheight(format);
if(usage & PIPE_TRANSFER_MAP_DIRECTLY)
{
/* No in-place transfer possible */
util_slab_free(&priv->transfer_pool, ptrans);
return NULL;
}
ptrans->base.stride = align(box->width, divSizeX) * util_format_get_blocksize(format); /* row stride in bytes */
ptrans->base.layer_stride = align(box->height, divSizeY) * ptrans->base.stride;
size_t size = ptrans->base.layer_stride * box->depth;
ptrans->buffer = MALLOC(size);
if(usage & PIPE_TRANSFER_READ)
{
/* untile or copy resource for reading */
if(resource_priv->layout == ETNA_LAYOUT_LINEAR || resource_priv->layout == ETNA_LAYOUT_TILED)
{
if(resource_priv->layout == ETNA_LAYOUT_TILED && !util_format_is_compressed(resource_priv->base.format))
{
etna_texture_untile(ptrans->buffer, mapped + ptrans->base.box.z * res_level->layer_stride,
ptrans->base.box.x, ptrans->base.box.y, res_level->stride,
ptrans->base.box.width, ptrans->base.box.height, ptrans->base.stride,
util_format_get_blocksize(resource_priv->base.format));
} else { /* non-tiled or compressed format */
util_copy_box(ptrans->buffer,
resource_priv->base.format,
ptrans->base.stride, ptrans->base.layer_stride,
0, 0, 0, /* dst x,y,z */
ptrans->base.box.width, ptrans->base.box.height, ptrans->base.box.depth,
mapped,
res_level->stride, res_level->layer_stride,
ptrans->base.box.x, ptrans->base.box.y, ptrans->base.box.z);
}
} else /* TODO supertiling */
{
BUG("unsupported tiling %i for reading", resource_priv->layout);
}
}
}
*out_transfer = &ptrans->base;
return ptrans->buffer;
}