/* ------------------------------------------------------------------------*//** * @FUNCTION tps659038_vsel_to_uv * @BRIEF for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. * @RETURNS voltage in microvolts corresponding to SMPS vsel command * @param[in] smps_id: voltage rail * @param[in] vsel: SMPS vsel command (in microvolts) * @DESCRIPTION for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. *//*------------------------------------------------------------------------ */ unsigned long tps659038_vsel_to_uv(unsigned char vsel) { unsigned long uv; unsigned int range; /* VSEL = 7-bit + range (MSB) */ range = extract_bit(vsel, 7); vsel = extract_bitfield(vsel, 0, TPS659038_VSEL_LEN); if (vsel == 0) { uv = 0; } else if (vsel <= 0x06) { uv = TPS659038_VOLT_MIN_UV; } else if (vsel >= 0x79) { uv = 1650000; } else { uv = TPS659038_VOLT_MIN_UV + (TPS659038_VSTEP_UV * (vsel - 6)); } /* Apply range multiplier */ uv = uv << range; dprintf("%s(%d, %d (0x%02X))=%lduV\n", __func__, smps_id, vsel, vsel, uv); return uv; }
/* ------------------------------------------------------------------------*//** * @FUNCTION clk_am335x_sysclk_rate_get * @BRIEF Return the mandatory system clock speed, in MHz. * @RETURNS > 0 system clock speed, in MHz. * OMAPCONF_ERR_CPU * OMAPCONF_ERR_UNEXPECTED * @param[in] none * @DESCRIPTION Return the mandatory system clock speed, in MHz. *//*------------------------------------------------------------------------ */ double clk_am335x_sysclk_rate_get(void) { unsigned int reg_val; static double sysclk = 0.0; sysclk_am335x_id sysclk_id; if (!cpu_is_am335x()) return (double) OMAPCONF_ERR_CPU; if (sysclk > 0.0) { dprintf("%s(): sysclk rate=%.1lfMHz\n", __func__, sysclk); return sysclk; } if (!mem_fake_access_get()) { mem_read(AM335X_STATUS, ®_val); sysclk_id = extract_bitfield(reg_val, 22, 2); } else { sysclk_id = SYSCLK_AM335X_19_2_MHZ; /* AM335X EVM PoR */ } sysclk = sysclk_am335x_rate_table[sysclk_id]; if (sysclk == 0.0) { fprintf(stderr, "%s(): bad CONTROL_STATUS value(%d)\n", __func__, sysclk_id); sysclk = (double) OMAPCONF_ERR_UNEXPECTED; } else { dprintf("%s(): CONTROL_STATUS=0x%x, sysclk rate=%.1lfMHz\n", __func__, sysclk_id, sysclk); } return sysclk; }
/* ------------------------------------------------------------------------*//** * @FUNCTION emu44xx_dependency_show * @BRIEF analyse dependency configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyse dependency configuration *//*------------------------------------------------------------------------ */ int emu44xx_dependency_show(FILE *stream) { unsigned int cm_dynamicdep; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) emu44xx_regtable_init(); if (mem_read(OMAP4430_CM_EMU_DYNAMICDEP, &cm_dynamicdep) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("OMAP4430_CM_EMU_DYNAMICDEP = 0x%08X\n", cm_dynamicdep); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| EMU Domain Dependency Configuration | Static | Dynamic |\n"); fprintf(stream, "|-------------------------------------|------------------|\n"); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L3_2", "", ((extract_bit(cm_dynamicdep, 6) == 1) ? "En" : "Dis")); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| %-44s | %-7d |\n", "Window Size", extract_bitfield(cm_dynamicdep, 24, 4)); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION vc44xx_cmdra_get * @BRIEF return Command Register Address (CMDRA) * @RETURNS >0 Command Register Address (CMDRA) * OMAPCONF_ERR_ARG * @param[in] id: voltage domain ID * @param[in] prm_vc_cfg_channel: PRM_VC_CFG_CHANNEL register content * @param[in] prm_vc_val_smps_ra_cmd: PRM_VC_VAL_SMPS_RA_CMD register * content * @DESCRIPTION return Command Register Address (CMDRA) *//*------------------------------------------------------------------------ */ short int vc44xx_cmdra_get(voltdm44xx_id id, unsigned int prm_vc_cfg_channel, unsigned int prm_vc_val_smps_ra_cmd) { short int cmdra; switch (id) { case OMAP4_VDD_MPU: cmdra = extract_bitfield(prm_vc_val_smps_ra_cmd, VC_CMDRA_VDD_MPU_L_POS, VC_CMDRA_VDD_MPU_L_LEN); break; case OMAP4_VDD_IVA: if (extract_bit(prm_vc_cfg_channel, VC_CFG_CHANNEL_RAC_VDD_IVA_L_POS) == 1) cmdra = extract_bitfield(prm_vc_val_smps_ra_cmd, VC_CMDRA_VDD_IVA_L_POS, VC_CMDRA_VDD_IVA_L_LEN); else cmdra = extract_bitfield(prm_vc_val_smps_ra_cmd, VC_CMDRA_VDD_CORE_L_POS, VC_CMDRA_VDD_CORE_L_LEN); break; case OMAP4_VDD_CORE: if (extract_bit(prm_vc_cfg_channel, VC_CFG_CHANNEL_RAC_VDD_CORE_L_POS) == 1) cmdra = extract_bitfield(prm_vc_val_smps_ra_cmd, VC_CMDRA_VDD_CORE_L_POS, VC_CMDRA_VDD_CORE_L_LEN); else cmdra = extract_bitfield(prm_vc_val_smps_ra_cmd, VC_CMDRA_VDD_MPU_L_POS, VC_CMDRA_VDD_MPU_L_LEN); break; default: cmdra = OMAPCONF_ERR_ARG; } return cmdra; }
/* ------------------------------------------------------------------------*//** * @FUNCTION vc44xx_sa_get * @BRIEF return Slave Address (SA) * @RETURNS >0 Slave Address (SA) * OMAPCONF_ERR_ARG * @param[in] id: voltage domain ID * @param[in] prm_vc_smps_sa: PRM_VC_SMPS_SA register content * @param[in] prm_vc_cfg_channel: PRM_VC_CFG_CHANNEL register content * @DESCRIPTION return Slave Address (SA) *//*------------------------------------------------------------------------ */ short int vc44xx_sa_get(voltdm44xx_id id, unsigned int prm_vc_smps_sa, unsigned int prm_vc_cfg_channel) { short int sa; switch (id) { case OMAP4_VDD_MPU: sa = extract_bitfield(prm_vc_smps_sa, VC_SA_VDD_MPU_L_POS, VC_SA_VDD_MPU_L_LEN); break; case OMAP4_VDD_IVA: if (extract_bit(prm_vc_cfg_channel, VC_CFG_CHANNEL_SA_VDD_IVA_L_POS) == 1) sa = extract_bitfield(prm_vc_smps_sa, VC_SA_VDD_IVA_L_POS, VC_SA_VDD_IVA_L_LEN); else sa = extract_bitfield(prm_vc_smps_sa, VC_SA_VDD_CORE_L_POS, VC_SA_VDD_CORE_L_LEN); break; case OMAP4_VDD_CORE: if (extract_bit(prm_vc_cfg_channel, VC_CFG_CHANNEL_SA_VDD_CORE_L_POS) == 1) sa = extract_bitfield(prm_vc_smps_sa, VC_SA_VDD_CORE_L_POS, VC_SA_VDD_CORE_L_LEN); else sa = extract_bitfield(prm_vc_smps_sa, VC_SA_VDD_MPU_L_POS, VC_SA_VDD_MPU_L_LEN); break; default: sa = OMAPCONF_ERR_ARG; } return sa; }
/* ------------------------------------------------------------------------*//** * @FUNCTION vc44xx_cmd_values_get * @BRIEF return ON/ONLP/RET/OFF command values * @RETURNS 0 in case of success * OMAPCONF_ERR_ARG * @param[in] id: voltage domain ID * @param[in,out] vc_regs: Voltage Controller registers content * @param[in,out] cmd_on: ON command value (RETURNED) * @param[in,out] cmd_onlp: ONLP command value (RETURNED) * @param[in,out] cmd_ret: RET command value (RETURNED) * @param[in,out] cmd_off: OFF command value (RETURNED) * @DESCRIPTION return ON/ONLP/RET/OFF command values * WARNING: CONSIDER PMIC-SPECIFIC SIZE OF COMMAND. *//*------------------------------------------------------------------------ */ short int vc44xx_cmd_values_get(voltdm44xx_id id, vc44xx_registers *vc_regs, unsigned char *cmd_on, unsigned char *cmd_onlp, unsigned char *cmd_ret, unsigned char *cmd_off) { int vsel_len, ret; ret = vc44xx_raw_cmd_values_get(id, vc_regs, cmd_on, cmd_onlp, cmd_ret, cmd_off); if (ret != 0) return ret; /* * Consider size of the commands (PMIC-dependent) * and mask it accordingly. */ vsel_len = smps_vsel_len_get(vdd_id2smps_id(id)); *cmd_on = extract_bitfield(*cmd_on, 0, vsel_len); *cmd_onlp = extract_bitfield(*cmd_onlp, 0, vsel_len); *cmd_ret = extract_bitfield(*cmd_ret, 0, vsel_len); *cmd_off = extract_bitfield(*cmd_off, 0, vsel_len); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_get_mode * @BRIEF retrieve module mode from PRCM register * @RETURNS 0 on success * OMAPCONF_ERR_ARG * OMAPCONF_ERR_CPU * @param[in] id: module ID * @param[in,out] mmode: module mode * @DESCRIPTION retrieve module mode from PRCM register *//*------------------------------------------------------------------------ */ int mod44xx_get_mode(mod44xx_id id, mod_module_mode *mmode) { unsigned int cm_clkctrl_addr, cm_clkctrl; int ret = 0; #ifdef MODULE44XX_DEBUG char name[MOD44XX_MAX_NAME_LENGTH]; #endif if ((mmode == NULL) || (id >= OMAP4_MODULE_ID_MAX)) { fprintf(stderr, "%s(): (mmode == NULL) || (id >= OMAP4_MODULE_ID_MAX)!!!\n", __func__); ret = OMAPCONF_ERR_ARG; goto mod44xx_get_mode_exit; } *mmode = MOD_MODULE_MODE_MAX; if (!cpu_is_omap44xx()) { fprintf(stderr, "%s(): cpu is not omap44xx!!!\n", __func__); ret = OMAPCONF_ERR_CPU; goto mod44xx_get_mode_exit; } /* Retrieve CM_CLKCTRL address */ cm_clkctrl_addr = (unsigned int) mod44xx_info_table[id].cm_clkctrl_addr; dprintf("%s(): module #%d name = %s CM_CLKCTRL ADDR = 0x%08X\n", __func__, id, mod44xx_get_name(id, name), cm_clkctrl_addr); /* Retrieve module mode */ if ((void *) cm_clkctrl_addr != NULL) { if (mem_read(cm_clkctrl_addr, &cm_clkctrl) != 0) { fprintf(stderr, "%s(): could not read register!!!\n", __func__); ret = OMAPCONF_ERR_REG_ACCESS; goto mod44xx_get_mode_exit; } *mmode = (mod_module_mode) extract_bitfield(cm_clkctrl, 0, 2); dprintf( "%s(): CM_CLKCTRL ADDR = 0x%08X CM_CLKCTRL = 0x%08X MODULEMODE = %d\n", __func__, cm_clkctrl_addr, cm_clkctrl, *mmode); ret = 0; } mod44xx_get_mode_exit: return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION twl603x_vsel_to_uv * @BRIEF for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. * @RETURNS voltage in microvolts corresponding to SMPS vsel command * @param[in] vdd_id: voltage rail * @param[in] vsel: SMPS vsel command (in microvolts) * @DESCRIPTION for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. *//*------------------------------------------------------------------------ */ unsigned long twl603x_vsel_to_uv(unsigned int vdd_id, unsigned char vsel) { unsigned long smps_offset, uv; unsigned int range; if (!twl603x_is_twl6035()) { if (vsel == 0) { uv = 0; } else if (vsel > 0x3E) { fprintf(stderr, "%s(): warning vsel (0x%02X) " "is reserved value, use max (0x3E) instead!\n", __func__, vsel); vsel = 0x3E; } smps_offset = twl603x_smps_offset_get(vdd_id); if (vsel >= 0x3A) uv = twl603x_data.smps_voltage_uv[vsel - 0x3A]; else uv = smps_offset + ((vsel - 1) * twl603x_data.vstep); } else { /* VSEL = 7-bit + range (MSB) */ range = extract_bit(vsel, 7); vsel = extract_bitfield(vsel, 0, 7); if (vsel == 0) { uv = 0; } else if (vsel <= 0x06) { uv = TWL6035_VOFFSET_UV; } else if (vsel >= 0x79) { uv = 1650000; } else { uv = TWL6035_VOFFSET_UV + (TWL6035_VSTEP_UV * (vsel - 6)); } /* Apply range multiplier */ uv = uv << range; } dprintf("%s(%d, %d (0x%02X))=%lduV\n", __func__, vdd_id, vsel, vsel, uv); return uv; }
/* ------------------------------------------------------------------------*//** * @FUNCTION tps65217x_vsel_to_uv * @BRIEF for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. * @RETURNS voltage in microvolts corresponding to SMPS vsel command * @param[in] smps_id: voltage rail * @param[in] vsel: SMPS vsel command (in microvolts) * @DESCRIPTION for a given rail, convert SMPS vsel command into voltage * in microvolts. Take into account SMPS voltage offset. *//*------------------------------------------------------------------------ */ unsigned long tps65217x_vsel_to_uv(unsigned char vsel) { unsigned long uv; vsel = extract_bitfield(vsel, 0, TPS65217X_VSEL_LEN); if (vsel == 0) { uv = TPS65217X_VOLT_MIN_UV; } else if (vsel >= 0x38) { uv = 3300000; } else if (vsel >= 0x18) { uv = TPS65217X_VOLT_MIN_UV + 600000 + (TPS65217X_VSTEP_UV * 2 * (vsel - 12)); } else { uv = TPS65217X_VOLT_MIN_UV + (TPS65217X_VSTEP_UV * vsel); } dprintf("%s(%d (0x%02X))=%lduV\n", __func__, vsel, vsel, uv); return uv; }
/* ------------------------------------------------------------------------*//** * @FUNCTION pwrdm54xx_config_show * @BRIEF decode and display power domain configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * @param[in,out] stream: output file * @param[in] id: valid power domain ID * @DESCRIPTION decode and display power domain configuration *//*------------------------------------------------------------------------ */ int pwrdm54xx_config_show(FILE *stream, pwrdm54xx_id id) { pwrdm_state st_last, st_curr, st_tgt; CHECK_CPU(54xx, OMAPCONF_ERR_CPU); CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG); CHECK_ARG_LESS_THAN(id, PWRDM54XX_ID_MAX, OMAPCONF_ERR_ARG); char s1[32], s2[32]; reg *pm_pwrstctrl_reg; reg *pm_pwrstst_reg; unsigned int pm_pwrstctrl; unsigned int pm_pwrstst; char s[64]; fprintf(stream, "|---------------------------------------------------" "-------------|\n"); strcpy(s, pwrdm54xx_name_get(id)); strcat(s, " Power Domain Configuration"); fprintf(stream, "| %-62s |\n", s); fprintf(stream, "|---------------------------------------------------" "-------------|\n"); fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Power State", "Current", "Target", "Last"); fprintf(stream, "|----------------------------------|---------|------" "---|---------|\n"); st_last = pwrdm54xx_state_get(id, PWRDM_STATE_PREVIOUS); st_curr = pwrdm54xx_state_get(id, PWRDM_STATE_CURRENT); st_tgt = pwrdm54xx_state_get(id, PWRDM_STATE_TARGET); fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Domain", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt), pwrdm_state_name_get(st_last)); if ((!pwrdm54xx_has_logic_ret_state_ctrl_bit(id)) && (!pwrdm54xx_has_pwrstst_reg(id))) goto pwrdm54xx_config_show_mem; st_tgt = pwrdm54xx_target_logic_ret_state_get(id); if (st_tgt != PWRDM_STATE_MAX) strcpy(s1, pwrdm_state_name_get(st_tgt)); else strcpy(s1, ""); st_curr = pwrdm54xx_logic_state_get(id); if (st_curr != PWRDM_STATE_MAX) strcpy(s2, pwrdm_state_name_get(st_curr)); else strcpy(s2, ""); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Logic", s2, s1); pwrdm54xx_config_show_mem: if (pwrdm54xx_has_pwrstctrl_reg(id)) { pm_pwrstctrl_reg = pwrdm54xx_pwrstctrl_reg_get(id); pm_pwrstctrl = reg_read(pm_pwrstctrl_reg); } if (pwrdm54xx_has_pwrstst_reg(id)) { pm_pwrstst_reg = pwrdm54xx_pwrstst_reg_get(id); pm_pwrstst = reg_read(pm_pwrstst_reg); } switch (id) { case PWRDM54XX_EMU: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " EMU bank", pwrdm_state_name_get(st_curr), ""); break; case PWRDM54XX_CAM: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " MEM", pwrdm_state_name_get(st_curr), ""); break; case PWRDM54XX_CORE: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 12, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 12); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " OCP_WP/UNIPRO1/DMM bank2", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 10, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 11); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " IPU S$", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " IPU L2RAM", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " OCMRAM", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " DMA/ICR/DMM bank1", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_DSS: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " MEM", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_L3_INIT: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " L3INIT bank2", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " L3INIT bank1", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_L4_PER: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " NONRETAINED bank", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " RETAINED bank", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_ABE: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " AESS", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " PERIPH", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_DSP: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " EDMA", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " L2$", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " L1$", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_GPU: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " MEM", pwrdm_state_name_get(st_curr), ""); break; case PWRDM54XX_IVA: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 10, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 11); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " TCM2", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " TCM1", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " SL2", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " HWA", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; case PWRDM54XX_MPU: fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Memory", "", ""); st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2); st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", " L2$", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt)); break; default: /* Nothing to print */ break; } if (pwrdm54xx_has_pwrstst_reg(id)) { fprintf(stream, "|---------------------------------------------" "-------------------|\n"); fprintf(stream, "| %-32s | %-27s |\n", "Ongoing Power Transition?", ((pwrdm54xx_in_transition(id) == 1) ? "YES" : "NO")); } fprintf(stream, "|---------------------------------------------------" "-------------|\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION dpll_settings_extract * @BRIEF extract DPLL settings from registers * @RETURNS 0 in case of success * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * @param[in] id: valid DPLL ID * @param[in] type: DPLL type * @param[in] dpll_regs: dpll registers to extract settings from * @param[in,out] settings: struct with extracted DPLL settings * @DESCRIPTION extract DPLL settings from registers *//*------------------------------------------------------------------------ */ int dpll_settings_extract(unsigned int id, dpll_type type, dpll_settings_regs *dpll_regs, dpll_settings *settings) { unsigned int val; CHECK_NULL_ARG(dpll_regs, OMAPCONF_ERR_ARG); CHECK_NULL_ARG(settings, OMAPCONF_ERR_ARG); settings->id = id; settings->type = type; /* Extract data from CM_CLKMODE_DPLL_xyz */ val = reg_read(dpll_regs->cm_clkmode_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clkmode_dpll)->name, val); settings->mode = extract_bitfield(val, 0, 3); (settings->ramp).ramp_level = extract_bitfield(val, 3, 2); (settings->ramp).ramp_rate = 1 << (extract_bitfield(val, 5, 3) + 1); settings->driftguard_en = extract_bit(val, 8); (settings->ramp).relock_ramp_en = extract_bit(val, 9); settings->lpmode_en = extract_bit(val, 10); settings->regm4xen = extract_bit(val, 11); (settings->SSC).mode = extract_bit(val, 12); (settings->SSC).ack = extract_bit(val, 13); (settings->SSC).downspread = extract_bit(val, 14); dprintf("%s(): mode=0x%X (%s), lp_mode=%u, REGM4XEN=%u, " "DRIFTGUARD_EN=%u\n", __func__, settings->mode, dpll_mode_name_get(settings->mode), settings->lpmode_en, settings->regm4xen, settings->driftguard_en); dprintf("%s(): RAMP_EN=%u, RAMP_RATE=%uxREFCLK, RAMP_LEVEL=%u (%s)\n", __func__, (settings->ramp).relock_ramp_en, (settings->ramp).ramp_rate, (settings->ramp).ramp_level, dpll_ramp_level_name_get((settings->ramp).ramp_level)); dprintf("%s(): SSC_EN=%u, SSC_ACK=%u, SSC_DOWNSPREAD=%u\n", __func__, (settings->SSC).mode, (settings->SSC).ack, (settings->SSC).downspread); /* Extract data from CM_IDLEST_DPLL_xyz */ val = reg_read(dpll_regs->cm_idlest_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_idlest_dpll)->name, val); settings->lock_status = extract_bit(val, 0); settings->mn_bypass_status = extract_bit(val, 8); dprintf("%s(): ST_DPLL_CLK=%u, ST_MN_BYPASS=%u\n", __func__, settings->lock_status, settings->mn_bypass_status); /* Extract data from CM_AUTOIDLE_DPLL_xyz */ val = reg_read(dpll_regs->cm_autoidle_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_autoidle_dpll)->name, val); settings->autoidle_mode = extract_bitfield(val, 0, 3); dprintf("%s(): AUTO_DPLL_MODE=%u (%s)\n", __func__, settings->autoidle_mode, dpll_autoidle_mode_name_get(settings->autoidle_mode)); /* Extract data from CM_CLKSEL_DPLL_xyz */ val = reg_read(dpll_regs->cm_clksel_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clksel_dpll)->name, val); if (settings->type == DPLL_TYPE_A) { (settings->MN).N = extract_bitfield(val, 0, 7); (settings->MN).M = extract_bitfield(val, 8, 11); settings->clkouthif_src = extract_bit(val, 20); if (!cpu_is_omap4430()) { (settings->DCC).en = extract_bit(val, 22); (settings->DCC).count = extract_bitfield(val, 24, 8); } else { (settings->DCC).en = 0; (settings->DCC).count = 0; } settings->bypass_clk = extract_bit(val, 23); } else { (settings->MN).N = extract_bitfield(val, 0, 8); (settings->MN).M = extract_bitfield(val, 8, 12); settings->selfreqdco = extract_bit(val, 21); settings->sd_div = extract_bitfield(val, 24, 8); dprintf("%s(): SELFREQDCO=%u, SD_DIV=%u\n", __func__, settings->selfreqdco, settings->sd_div); } dprintf("%s(): M=%u, N=%u, CLKOUTHIF_CLK=%u, BP_CLK=%u\n", __func__, (settings->MN).M, (settings->MN).N, settings->clkouthif_src, settings->bypass_clk); dprintf("%s(): DCC_EN=%u, DCC_COUNT=%u\n", __func__, (settings->DCC).en, (settings->DCC).count); /* Extract data from CM_BYPCLK_DPLL_XYZ */ if ((void *) dpll_regs->cm_bypclk_dpll != NULL) { val = reg_read(dpll_regs->cm_bypclk_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_bypclk_dpll)->name, val); settings->bypass_clk_div = 1 << extract_bitfield(val, 0, 2); dprintf("%s(): BP_CLK_DIV=%u\n", __func__, settings->bypass_clk_div); } else { settings->bypass_clk_div = 1; dprintf("%s(): BYPCLK register does not exist.\n", __func__); } /* Extract data from CM_DIV_M2_DPLL_XYZ */ if ((void *) dpll_regs->cm_div_m2_dpll != NULL) { val = reg_read(dpll_regs->cm_div_m2_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_div_m2_dpll)->name, val); (settings->MN).M2_present = 1; if (settings->type == DPLL_TYPE_A) { (settings->MN).M2 = extract_bitfield(val, 0, 5); (settings->MN).X2_M2_autogating = !extract_bit(val, 10); (settings->MN).X2_M2_clkout_st = extract_bit(val, 11); } else { (settings->MN).M2 = extract_bitfield(val, 0, 7); } (settings->MN).M2_autogating = !extract_bit(val, 8); (settings->MN).M2_clkout_st = extract_bit(val, 9); dprintf("%s(): M2 DIV=%u, AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).M2, (settings->MN).M2_autogating, (settings->MN).M2_clkout_st); if (settings->type == DPLL_TYPE_A) { dprintf("%s(): X2_M2 AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).X2_M2_autogating, (settings->MN).X2_M2_clkout_st); } } else { (settings->MN).M2_present = 0; dprintf("%s(): DIV_M2 register does not exist.\n", __func__); } /* Extract data from CM_DIV_M3_DPLL_XYZ */ if ((void *) dpll_regs->cm_div_m3_dpll != NULL) { val = reg_read(dpll_regs->cm_div_m3_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_div_m3_dpll)->name, val); (settings->MN).M3_present = 1; (settings->MN).M3 = extract_bitfield(val, 0, 5); (settings->MN).X2_M3_autogating = !extract_bit(val, 8); (settings->MN).X2_M3_clkout_st = extract_bit(val, 9); dprintf("%s(): X2_M3 DIV=%u, AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).M3, (settings->MN).X2_M3_autogating, (settings->MN).X2_M3_clkout_st); } else { (settings->MN).M3_present = 0; dprintf("%s(): DIV_M3 register does not exist.\n", __func__); } /* Extract data from CM_DELTAMSTEP_DPLL_xyz */ val = reg_read(dpll_regs->cm_ssc_deltamstep_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_ssc_deltamstep_dpll)->name, val); (settings->SSC).deltaMStep = extract_bitfield(val, 0, 20); dprintf("%s(): deltaMStep=0x%X\n", __func__, (settings->SSC).deltaMStep); /* Extract data from CM_MODFREQDIV_DPLL_xyz */ val = reg_read(dpll_regs->cm_ssc_modfreqdiv_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_ssc_modfreqdiv_dpll)->name, val); (settings->SSC).mantissa = extract_bitfield(val, 0, 7); (settings->SSC).exponent = extract_bitfield(val, 8, 3); dprintf("%s(): mantissa=0x%X, exponent=0x%X\n", __func__, (settings->SSC).mantissa, (settings->SSC).exponent); /* Extract data from CM_CLKDCOLDO_DPLL_xyz */ if ((void *) dpll_regs->cm_clkdcoldo_dpll != NULL) { val = reg_read(dpll_regs->cm_clkdcoldo_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clkdcoldo_dpll)->name, val); (settings->MN).clkdcoldo_autogating = !extract_bit(val, 8); (settings->MN).clkdcoldo_clkout_st = extract_bit(val, 9); dprintf("%s(): CLKDCOLDO AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).clkdcoldo_autogating, (settings->MN).clkdcoldo_clkout_st); } return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_dependency_show * @BRIEF analyse MPU dependency configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyse MPU dependency configuration *//*------------------------------------------------------------------------ */ int mpu44xx_dependency_show(FILE *stream) { unsigned int cm_mpu_staticdep; unsigned int cm_mpu_dynamicdep; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) mpu44xx_regtable_init(); if (mem_read(OMAP4430_CM_MPU_STATICDEP, &cm_mpu_staticdep) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_MPU_DYNAMICDEP, &cm_mpu_dynamicdep) != 0) return OMAPCONF_ERR_REG_ACCESS; fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| MPU Domain Dependency Configuration | Static | Dynamic |\n"); fprintf(stream, "|-------------------------------------|------------------|\n"); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "MPU_M3", ((extract_bit(cm_mpu_staticdep, 0) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 0) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "DSP", ((extract_bit(cm_mpu_staticdep, 1) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 1) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "IVAHD", ((extract_bit(cm_mpu_staticdep, 2) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 2) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "ABE", ((extract_bit(cm_mpu_staticdep, 3) == 1) ? "En" : "Dis"), "En"); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "MEM IF", ((extract_bit(cm_mpu_staticdep, 4) == 1) ? "En" : "Dis"), "En"); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L3_1", ((extract_bit(cm_mpu_staticdep, 5) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 5) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L3_2", ((extract_bit(cm_mpu_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 6) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L3INIT", ((extract_bit(cm_mpu_staticdep, 7) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 7) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "DSS", ((extract_bit(cm_mpu_staticdep, 8) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 8) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "ISS", ((extract_bit(cm_mpu_staticdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 9) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "GFX", ((extract_bit(cm_mpu_staticdep, 10) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 10) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "SDMA", "Dis", ((extract_bit(cm_mpu_dynamicdep, 11) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L4CFG", ((extract_bit(cm_mpu_staticdep, 12) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 12) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L4PER", ((extract_bit(cm_mpu_staticdep, 13) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 13) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L4SEC", ((extract_bit(cm_mpu_staticdep, 14) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 14) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L4WKUP", ((extract_bit(cm_mpu_staticdep, 15) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_dynamicdep, 15) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "ALWONCORE", "Dis", ((extract_bit(cm_mpu_dynamicdep, 16) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "CEFUSE", "Dis", ((extract_bit(cm_mpu_dynamicdep, 17) == 1) ? "En" : "Dis")); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "C2C", "Dis", ((extract_bit(cm_mpu_dynamicdep, 18) == 1) ? "En" : "Dis")); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| %-44s | %-7d |\n", "Window Size", extract_bitfield(cm_mpu_dynamicdep, 24, 4)); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_config_show * @BRIEF analyze MPU power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze MPU power configuration *//*------------------------------------------------------------------------ */ int mpu44xx_config_show(FILE *stream) { unsigned int pm_pda_cpu0_pwrstctrl; unsigned int pm_pda_cpu0_pwrstst; unsigned int rm_pda_cpu0_context; unsigned int cm_pda_cpu0_clkctrl; unsigned int cm_pda_cpu0_clkstctrl; unsigned int pm_pda_cpu1_pwrstctrl; unsigned int pm_pda_cpu1_pwrstst; unsigned int rm_pda_cpu1_context; unsigned int cm_pda_cpu1_clkctrl; unsigned int cm_pda_cpu1_clkstctrl; unsigned int scu_cpu_power_status; char s0[32], s1[32]; unsigned int cm_clkmode_dpll_mpu; unsigned int cm_idlest_dpll_mpu; unsigned int cm_autoidle_dpll_mpu; omap4_dpll_params dpll_mpu_params; unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) mpu44xx_regtable_init(); if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTCTRL, &pm_pda_cpu0_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTST, &pm_pda_cpu0_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT, &rm_pda_cpu0_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL, &cm_pda_cpu0_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CLKSTCTRL, &cm_pda_cpu0_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTCTRL, &pm_pda_cpu1_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTST, &pm_pda_cpu1_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT, &rm_pda_cpu1_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL, &cm_pda_cpu1_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CLKSTCTRL, &cm_pda_cpu1_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_SCU_CPU_POWER_STATUS, &scu_cpu_power_status) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_CLKMODE_DPLL_MPU, &cm_clkmode_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_IDLEST_DPLL_MPU, &cm_idlest_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_AUTOIDLE_DPLL_MPU, &cm_autoidle_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = dpll44xx_dpll_params_get(DPLL44XX_MPU, &dpll_mpu_params, 0); if (ret < 0) return ret; /* MPU LPRM config */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "MPU LPRM Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Logic State", ((extract_bit(pm_pda_cpu0_pwrstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstst, 2) == 1) ? "ON" : "OFF")); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 4, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 4, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current L1$ State", s0, s1); pwrdm_state2string(s0, (pwrdm_state)extract_bitfield(pm_pda_cpu0_pwrstctrl, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstctrl, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Standby Status", ((extract_bit(cm_pda_cpu0_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING"), ((extract_bit(cm_pda_cpu1_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Target Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Logic State When Domain is RET", ((extract_bit(pm_pda_cpu0_pwrstctrl, 2) == 1) ? "RET" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstctrl, 2) == 1) ? "RET" : "OFF")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Clock Control", clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu0_clkstctrl, 0, 2)), clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu1_clkstctrl, 0, 2))); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 24, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 24, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last Power State", s0, s1); } fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last L1$ Context", ((extract_bit(rm_pda_cpu0_context, 8) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 8) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last CPU Context", ((extract_bit(rm_pda_cpu0_context, 0) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 0) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\n"); /* SCU Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "SCU Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s0, extract_bitfield(scu_cpu_power_status, 0, 2)); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s1, extract_bitfield(scu_cpu_power_status, 8, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "CPU Power Status", s0, s1); fprintf(stream, "|---------------------------------------------------" "-----|\n"); fprintf(stream, "\n"); /* MPU Power Domain Configuration */ if (mem_read(OMAP4430_PM_MPU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_MPU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "MPU", OMAP4430_PM_MPU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_MPU_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* MPU Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MPU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MPU Module Power Configuration */ if (mem_read(OMAP4430_CM_MPU_MPU_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MPU_MPU_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_MPU_CLKCTRL, cm_clkctrl, OMAP4430_RM_MPU_MPU_CONTEXT, rm_context); if (ret != 0) return ret; /* MPU DPLL Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| MPU DPLL Configuration " " |\n"); fprintf(stream, "|--------------------------------|-------------------" "----|\n"); fprintf(stream, "| %-30s | %-21s |\n", "Status", dpll_status_name_get((dpll_status) dpll_mpu_params.status)); sprintf(s0, "%d", (unsigned int) dpll_mpu_params.M2_speed); fprintf(stream, "| %-30s | %-21s |\n", "Clock Speed (MHz)", s0); fprintf(stream, "| %-30s | %-21s |\n", "Mode", dpll_mode_name_get((dpll_mode) dpll_mpu_params.mode)); fprintf(stream, "| %-30s | %-21s |\n", "Low-Power Mode", (dpll_mpu_params.lpmode == 1) ? "Enabled" : "Disabled"); fprintf(stream, "| %-30s | %-21s |\n", "Autoidle Mode", dpll_autoidle_mode_name_get((dpll_autoidle_mode) dpll_mpu_params.autoidle_mode)); fprintf(stream, "| %-30s | %-21s |\n", "M2 Output Autogating", (dpll_mpu_params.M2_autogating == 1) ? "Enabled" : "Disabled"); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\nNB: type \"omapconf dplls cfg\" " "for detailed DPLL configuration.\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION clk_am335x_rate_get * @BRIEF convert bitfield value from register into string * @RETURNS > 0 clock speed in MHz * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * @param[in] clk_id: am335x clock id * @param[in] ignore: do not consider DPLL stop status. * Useful for functions that needs the DPLL output * frequencies whatever its status * (e.g. audit, clock tree, etc) * @DESCRIPTION convert bitfield value from register into string *//*------------------------------------------------------------------------ */ double clk_am335x_rate_get(clk_am335x_id clk_id, unsigned short ignore) { unsigned int reg_val; double src_clk_speed, out_clk_speed; clk_am335x_id src_clk_id; double div; if (!cpu_is_am335x()) return (double) OMAPCONF_ERR_CPU; switch (clk_id) { /* 32K CLKS */ case CLK_AM335X_CLK_32KHZ: mem_read(AM335X_CLK32K_DIVRATIO_CTRL, ®_val); if (extract_bit(reg_val, 0) == 0) div = 732.4219; else div = 366.2109; src_clk_id = CLK_AM335X_CLK_24; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / div; DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div, out_clk_speed); return out_clk_speed; case CLK_AM335X_CLK_RC32K: out_clk_speed = AM335X_SYS_32K_SPEED; DPRINT_CLK_SPEED1(clk_id, out_clk_speed); return out_clk_speed; case CLK_AM335X_CLK_32K_RTC: out_clk_speed = AM335X_EXT_32K_SPEED; DPRINT_CLK_SPEED1(clk_id, out_clk_speed); return out_clk_speed; /* SYS CLKS */ case CLK_AM335X_SYS_CLK: /* Listed as M_OSC (Master Oscillator) in TRM */ out_clk_speed = clk_am335x_sysclk_rate_get(); DPRINT_CLK_SPEED1(clk_id, out_clk_speed); return out_clk_speed; case CLK_AM335X_TCLKIN: out_clk_speed = AM335X_TCLKIN_SPEED; DPRINT_CLK_SPEED1(clk_id, out_clk_speed); return out_clk_speed; case CLK_AM335X_CLK_48: src_clk_id = CLK_AM335X_PER_CLKOUTM2; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 4; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_CLK_24: src_clk_id = CLK_AM335X_CLK_48; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_MHZ_250_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM5; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_MHZ_125_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM5; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_MHZ_50_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM5; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 5; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_MHZ_5_CLK: src_clk_id = CLK_AM335X_MHZ_50_CLK; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 10; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; /* DPLL CORE OUTPUT CLKS */ case CLK_AM335X_CORE_CLKOUTM4: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M4, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M4", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_CORE_CLKOUTM5: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M5, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M5", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_CORE_CLKOUTM6: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M6, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M6", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_SGX_CORECLK: reg_val = reg_read(&am335x_clksel_gfx_fclk); if (extract_bit(reg_val, 1) == 0) src_clk_id = CLK_AM335X_CORE_CLKOUTM4; else src_clk_id = CLK_AM335X_PER_CLKOUTM2; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); div = (double) (1 << extract_bit(reg_val, 0)); out_clk_speed = src_clk_speed / div; DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div, out_clk_speed); return out_clk_speed; case CLK_AM335X_L3S_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_L4_PER_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_L4_WKUPCLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_L3F_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_L4F_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_PRU_ICSS_IEP_CLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_DEBUGSS_CLKA: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_PRU_ICSS_OCP_CLKL: reg_val = reg_read(&am335x_clksel_pru_icss_ocp_clk); if (extract_bit(reg_val, 0) == 0) src_clk_id = CLK_AM335X_CORE_CLKOUTM4; else src_clk_id = CLK_AM335X_DISP_CLKOUT; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_CPTS_RFT_CLK: reg_val = reg_read(&am335x_cm_cpts_rft_clksel); if (extract_bit(reg_val, 0) == 0) src_clk_id = CLK_AM335X_CORE_CLKOUTM4; else src_clk_id = CLK_AM335X_CORE_CLKOUTM5; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; /* DPLL PER OUTPUT CLKS */ case CLK_AM335X_USB_PHY_CLK: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_PER, DPLL_AM335X_CLKDCOLDO, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_PER CLKOUT", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_PER_CLKOUTM2: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_PER, DPLL_AM335X_CLKOUT, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_PER CLKOUT", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_PRU_ICSS_UART_CLK: src_clk_id = CLK_AM335X_PER_CLKOUTM2; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_MMC_CLK: src_clk_id = CLK_AM335X_PER_CLKOUTM2; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_SPI_CLK: src_clk_id = CLK_AM335X_CLK_48; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_UART_CLK: src_clk_id = CLK_AM335X_CLK_48; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_I2C_CLK: src_clk_id = CLK_AM335X_CLK_48; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; /* DPLL MPU OUTPUT CLKS */ case CLK_AM335X_MPU_CLK: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_MPU, DPLL_AM335X_CLKOUT, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_MPU CLKOUT", src_clk_speed, out_clk_speed); return out_clk_speed; /* DPLL DISP OUTPUT CLKS */ case CLK_AM335X_DISP_CLKOUT: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_DISP, DPLL_AM335X_CLKOUT, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_DISP CLKOUT", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_LCD_CLK: reg_val = reg_read(&am335x_clksel_lcdc_pixel_clk); if (extract_bitfield(reg_val, 0, 2) == 2) src_clk_id = CLK_AM335X_PER_CLKOUTM2; else if (extract_bitfield(reg_val, 0, 2) == 1) src_clk_id = CLK_AM335X_CORE_CLKOUTM5; else src_clk_id = CLK_AM335X_DISP_CLKOUT; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; /* DPLL DDR OUTPUT CLKS */ case CLK_AM335X_DDR_CLKOUTM2: src_clk_speed = dpll_am335x_output_rate_get( DPLL_AM335X_DDR, DPLL_AM335X_CLKOUT, ignore); out_clk_speed = src_clk_speed; DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_DDR CLKOUT", src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_EMIF_M_CLK: src_clk_id = CLK_AM335X_DDR_CLKOUTM2; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_GFX_SYSCLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_GFX_MEMCLK: src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); out_clk_speed = src_clk_speed / 2; DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed, out_clk_speed); return out_clk_speed; case CLK_AM335X_GFX_CORECLK: reg_val = reg_read(&am335x_clksel_gfx_fclk); if (extract_bit(reg_val, 1)) src_clk_id = CLK_AM335X_PER_CLKOUTM2; else src_clk_id = CLK_AM335X_CORE_CLKOUTM4; src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore); if (extract_bit(reg_val, 0)) div = 2; else div = 1; out_clk_speed = src_clk_speed / div; DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div, out_clk_speed); return out_clk_speed; case CLK_AM335X_ID_MAX: out_clk_speed = 0; DPRINT_CLK_SPEED1(clk_id, out_clk_speed); return out_clk_speed; default: fprintf(stderr, "%s(): invalid clock id %s(%u)!\n", __func__, clk_am335x_name_table[clk_id], clk_id); return (double) OMAPCONF_ERR_ARG; } return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION core44xx_dependency_show * @BRIEF analyse CORE dependency configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in, out] stream: output file stream * @DESCRIPTION analyse CORE dependency configuration *//*------------------------------------------------------------------------ */ int core44xx_dependency_show(FILE *stream) { unsigned int cm_l3_1_dynamicdep; unsigned int cm_l3_2_dynamicdep; unsigned int cm_mpu_m3_staticdep; unsigned int cm_mpu_m3_dynamicdep; unsigned int cm_sdma_staticdep; unsigned int cm_sdma_dynamicdep; unsigned int cm_c2c_staticdep; unsigned int cm_c2c_dynamicdep; unsigned int cm_l4cfg_dynamicdep; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) core44xx_regtable_init(); ret = mem_read(OMAP4430_CM_L3_1_DYNAMICDEP, &cm_l3_1_dynamicdep); ret += mem_read(OMAP4430_CM_L3_2_DYNAMICDEP, &cm_l3_2_dynamicdep); ret += mem_read(OMAP4430_CM_MPU_M3_STATICDEP, &cm_mpu_m3_staticdep); ret += mem_read(OMAP4430_CM_MPU_M3_DYNAMICDEP, &cm_mpu_m3_dynamicdep); ret += mem_read(OMAP4430_CM_SDMA_STATICDEP, &cm_sdma_staticdep); ret += mem_read(OMAP4430_CM_SDMA_DYNAMICDEP, &cm_sdma_dynamicdep); ret += mem_read(OMAP4430_CM_C2C_STATICDEP, &cm_c2c_staticdep); ret += mem_read(OMAP4430_CM_C2C_DYNAMICDEP, &cm_c2c_dynamicdep); ret += mem_read(OMAP4430_CM_L4CFG_DYNAMICDEP, &cm_l4cfg_dynamicdep); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| CORE Domain Dependency Configuration (Static/Dynamic) " " |\n"); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| | FROM: " " |\n"); fprintf(stream, "| | L3_1 | L3_2 | MPU_M3 | SDMA | C2C" " | L4CFG |\n"); fprintf(stream, "| |Stat|Dyn |Stat|Dyn |Stat|Dyn |Stat|Dyn |Stat|" "Dyn |Stat|Dyn |\n"); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| TOWARDS: | | | | | | | | | | " " | | |\n"); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "MPU_M3", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 0) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 0) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "DSP", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 1) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 1) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "IVAHD", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 2) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ABE", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "MEM IF", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 4) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_dynamicdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 4) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3_1", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 5) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 5) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3_2", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 6) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_dynamicdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_dynamicdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_dynamicdep, 6) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 6) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3INIT", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 7) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 7) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "DSS", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 8) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 8) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 8) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 8) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ISS", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_dynamicdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_staticdep, 9) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 9) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "GFX", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 10) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 10) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "SDMA", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 11) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 11) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4CFG", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4PER", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 13) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4SEC", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 14) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 14) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 14) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4WKUP", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 15) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 15) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 15) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ALWONCORE", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 16) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 16) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "CEFUSE", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 17) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 17) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "C2C", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 18) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 18) == 1) ? "En" : "Dis")); if (!cpu_is_omap4430()) fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|" "%-3s | %-3s|%-3s | %-3s|%-3s |\n", "MPU", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 19) == 1) ? "En" : "Dis")); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| Dynamic Dep | | | | | " " | |\n"); fprintf(stream, "| %-12s | %-2d | %-2d | %-2d | | " "%-2d | %-2d |\n", "Window Size", extract_bitfield(cm_l3_1_dynamicdep, 24, 4), extract_bitfield(cm_l3_2_dynamicdep, 24, 4), extract_bitfield(cm_mpu_m3_dynamicdep, 24, 4), extract_bitfield(cm_c2c_dynamicdep, 24, 4), extract_bitfield(cm_l4cfg_dynamicdep, 24, 4)); fprintf(stream, "|------------------------------------------------------------" "--------------|\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION pwrdm44xx_config_show * @BRIEF analyze power domain configuration * @RETURNS 0 in case of error * @param[in,out] stream: output file * @param[in,out] name: domain name * @param[in] pm_pwstctrl_addr: PM_xyz_PWSTCTRL register address * @param[in] pm_pwstctrl: PM_xyz_PWSTCTRL register content * @param[in] pm_pwstst_addr: PM_xyz_PWSTST register address * @param[in] pm_pwstst: PM_xyz_PWSTST register content * @DESCRIPTION analyze power domain configuration *//*------------------------------------------------------------------------ */ int pwrdm44xx_config_show(FILE *stream, const char name[11], unsigned int pm_pwstctrl_addr, unsigned int pm_pwstctrl, unsigned int pm_pwstst_addr, unsigned int pm_pwstst) { char curr[32], tgt[32], last[32]; dprintf("%s(): name=%s\n", __func__, name); dprintf("%s(): pm_pwstctrl addr=0x%08X\n", __func__, pm_pwstctrl_addr); dprintf("%s(): pm_pwstctrl=0x%08X\n", __func__, pm_pwstctrl); dprintf("%s(): pm_pwstst addr=0x%08X\n", __func__, pm_pwstst_addr); dprintf("%s(): pm_pwstst=0x%08X\n", __func__, pm_pwstst); dprintf("\n"); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-10s Power Domain Configuration " " |\n", name); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Power State", "Current", "Target", "Last"); fprintf(stream, "|--------------------------------|---------|--------" "-|---------|\n"); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 0, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 0, 2)); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { switch (pm_pwstst_addr) { case OMAP4430_PM_MPU_PWRSTST: case OMAP4430_PM_DSP_PWRSTST: case OMAP4430_PM_ABE_PWRSTST: case OMAP4430_PM_CORE_PWRSTST: case OMAP4430_PM_IVAHD_PWRSTST: case OMAP4430_PM_L3INIT_PWRSTST: case OMAP4430_PM_L4PER_PWRSTST: pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); break; case OMAP4430_PM_CAM_PWRSTST: case OMAP4430_PM_DSS_PWRSTST: case OMAP4430_PM_GFX_PWRSTST: case OMAP4430_PM_EMU_PWRSTST: if (!cpu_is_omap4430()) pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); else strcpy(last, ""); break; default: strcpy(last, ""); } } else { strcpy(last, ""); } fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Domain", curr, tgt, last); if ((pm_pwstctrl_addr == OMAP4430_PM_CAM_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_EMU_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_GFX_PWRSTCTRL)) { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ""); } else { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pwstctrl, 2) == 1) ? "RET" : "OFF")); } fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Memory", "", ""); switch (pm_pwstctrl_addr) { case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 12, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 12)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCP_WP Bank & DMM Bank2", curr, tgt); break; default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM2", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 Unicache", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RAM", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EDMA", curr, tgt); break; case OMAP4430_PM_DSS_PWRSTCTRL: case OMAP4430_PM_CAM_PWRSTCTRL: case OMAP4430_PM_GFX_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MEM", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM1", curr, tgt); case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 L2 RAM", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_ABE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " PERIPHMEM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " AESSMEM", curr, tgt); break; case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); if (cpu_is_omap4430()) pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); else strcpy(curr, ""); /* not available on OMAP44[60-70] */ pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " SL2", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " HWA", curr, tgt); break; case OMAP4430_PM_L4PER_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " NONRETAINED", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RETAINED", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCM RAM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " DMA/ICR Bank & DMM Bank1", curr, tgt); break; case OMAP4430_PM_L3INIT_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L3INIT Bank1", curr, tgt); break; case OMAP4430_PM_EMU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 16, 2)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EMU Bank", curr, tgt); break; default: break; } fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-27s |\n", "Ongoing Power Transition?", ((extract_bit(pm_pwstst, 20) == 1) ? "YES" : "NO")); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_get_standby_mode * @BRIEF retrieve omap module's standby mode * @RETURNS 1 if success * 0 if omap module's registers NOT accessible * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_CPU * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_INTERNAL * @param[in] module_id: omap module ID * @param[in,out] mode: returned omap module's standby mode * @DESCRIPTION retrieve omap module's standby mode *//*------------------------------------------------------------------------ */ int mod44xx_get_standby_mode(mod44xx_id module_id, mod_standby_mode *mode) { int ret_val = 0; unsigned int sysconfig; mod_interface_type type; char name[MOD44XX_MAX_NAME_LENGTH]; *mode = MOD_STANDBY_MODE_MAX; if (!cpu_is_omap44xx()) { fprintf(stderr, "%s(): unsupported cpu!!!\n", __func__); ret_val = OMAPCONF_ERR_CPU; goto mod44xx_get_standby_mode_end; } if (module_id >= OMAP4_MODULE_ID_MAX) { fprintf(stderr, "%s(): incorrect module id!!! (%u)\n", __func__, module_id); ret_val = OMAPCONF_ERR_ARG; goto mod44xx_get_standby_mode_end; } mod44xx_get_interface_type(module_id, &type); if ((module_id != OMAP4_MPU_M3) && (type != MOD_INTERFACE_MASTER) && (type != MOD_INTERFACE_DUAL)) { dprintf("%s(): module #%d name = %s has no master interface\n", __func__, module_id, mod44xx_get_name(module_id, name)); ret_val = OMAPCONF_ERR_NOT_AVAILABLE; goto mod44xx_get_standby_mode_end; } ret_val = mod44xx_is_accessible(module_id); if (ret_val == 0) { /* Module is NOT accessible */ ret_val = 0; dprintf("%s(): module #%d name = %s is NOT accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); goto mod44xx_get_standby_mode_end; } else if (ret_val != 1) { /* Internal error */ dprintf("%s(): mod44xx_is_accessible() returned with %d!!!\n", __func__, ret_val); goto mod44xx_get_standby_mode_end; } /* Module is accessible */ dprintf("%s(): module #%d name = %s is accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); if ((module_id != OMAP4_MPU_M3) && (mod44xx_info_table[module_id].sysconfig_addr == NULL)) { fprintf(stderr, "%s(): error module %s interface type is not NONE but SYSCONFIG ADDR == NULL\n", __func__, mod44xx_get_name(module_id, name)); ret_val = OMAPCONF_ERR_INTERNAL; goto mod44xx_get_standby_mode_end; } if (module_id != OMAP4_MPU_M3) { OMAP_READREG((unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); dprintf("%s(): SYSCONFIG ADDR = 0x%08X SYSCONFIG = 0x%08X\n", __func__, (unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); } else { OMAP_READREG((unsigned int) OMAP4430_STANDBY_CORE_SYSCONFIG, sysconfig); dprintf( "%s(): SYSCONFIG ADDR = 0x%08X, STANDBY_CORE_SYSCONFIG = 0x%08X\n", __func__, (unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG, sysconfig); } /* Check module's standby mode */ switch (module_id) { case OMAP4_IVAHD: case OMAP4_ICONT1: case OMAP4_ICONT2: case OMAP4_VDMA: case OMAP4_IME3: case OMAP4_ILF3: case OMAP4_AESS: case OMAP4_ISP5: case OMAP4_SIMCOP: case OMAP4_SIMCOP_DMA: case OMAP4_FDIF: case OMAP4_GFX: case OMAP4_MMC1_HL: case OMAP4_MMC2_HL: case OMAP4_MMC3_HL: case OMAP4_MMC4_HL: case OMAP4_MMC5_HL: case OMAP4_UNIPRO1: case OMAP4_FSUSBHOST: case OMAP4_HSUSBHOST: case OMAP4_ISS: *mode = (mod_standby_mode) extract_bitfield(sysconfig, 4, 2); ret_val = 1; dprintf("%s(): module %s standby mode (bits [5:4])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; case OMAP4_MPU_M3: *mode = (mod_standby_mode) extract_bitfield(sysconfig, 0, 2); ret_val = 1; dprintf("%s(): module %s standby mode (bits [0:12])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; default: *mode = (mod_standby_mode) extract_bitfield(sysconfig, 12, 2); ret_val = 1; dprintf("%s(): module %s standby mode (bits [13:12])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); } mod44xx_get_standby_mode_end: return ret_val; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_get_idle_status * @BRIEF retrieve module's idle status from CM_xxx_xxx_CLKCTRL * @RETURNS module idle status * MOD_IDLE_STATUS_MAX in case of error * @param[in] id: module ID * @param[in,out] idlest: returned module idle status (string) * @DESCRIPTION retrieve module's idle status from CM_xxx_xxx_CLKCTRL *//*------------------------------------------------------------------------ */ mod_idle_status mod44xx_get_idle_status(mod44xx_id id, char idlest[14]) { mod_idle_status ret = MOD_IDLE_STATUS_MAX; unsigned int cm_clkctrl; #ifdef MODULE44XX_DEBUG char name[MOD44XX_MAX_NAME_LENGTH]; #endif if (idlest == NULL) { fprintf(stderr, "%s(): idlest == NULL!\n", __func__); goto mod44xx_get_idle_status_end; } *idlest = '\0'; if (id >= OMAP4_MODULE_ID_MAX) { fprintf(stderr, "%s(): id (%u) >= OMAP4_MODULE_ID_MAX!\n", __func__, id); goto mod44xx_get_idle_status_end; } if (mod44xx_info_table[id].cm_clkctrl_addr == NULL) { dprintf("%s(): %s has no CLKCTRL register\n", __func__, mod44xx_get_name(id, name)); goto mod44xx_get_idle_status_end; } if (mem_read((unsigned int) mod44xx_info_table[id].cm_clkctrl_addr, &cm_clkctrl) != 0) { fprintf(stderr, "%s(): error reading CLKCTRL reg (@0x%08X)!\n", __func__, (unsigned int) mod44xx_info_table[id].cm_clkctrl_addr); goto mod44xx_get_idle_status_end; } dprintf( "%s(): CM_CLKCTRL ADDR = 0x%08X, CM_CLKCTRL = 0x%08X, IDLEST = %u\n", __func__, (unsigned int) mod44xx_info_table[id].cm_clkctrl_addr, cm_clkctrl, extract_bitfield(cm_clkctrl, 16, 2)); switch (extract_bitfield(cm_clkctrl, 16, 2)) { case 0: strcpy(idlest, "Full ON"); ret = MOD_FULL_ON; break; case 1: strcpy(idlest, "In Transition"); ret = MOD_IN_TRANSITION; break; case 2: strcpy(idlest, "OCP-ONLY Idle"); ret = MOD_OCP_ONLY_IDLE; break; case 3: strcpy(idlest, "Disabled"); ret = MOD_DISABLED; break; default: fprintf(stderr, "%s(): error decoding idle status!\n", __func__); } dprintf("%s(): %s idle status is %s (%u)\n", __func__, mod44xx_get_name(id, name), idlest, extract_bitfield(cm_clkctrl, 16, 2)); mod44xx_get_idle_status_end: return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_get_idle_mode * @BRIEF retrieve omap module's idle mode * @RETURNS 1 if success * 0 if omap module's registers NOT accessible * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_CPU * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_INTERNAL * @param[in] module_id: omap module ID * @param[in,out] mode: returned omap module's idle mode * @DESCRIPTION retrieve omap module's idle mode *//*------------------------------------------------------------------------ */ int mod44xx_get_idle_mode(mod44xx_id module_id, mod_idle_mode *mode) { int ret_val = 0; unsigned int sysconfig; mod_interface_type type; char name[MOD44XX_MAX_NAME_LENGTH]; *mode = MOD_IDLE_MODE_MAX; if (!cpu_is_omap44xx()) { fprintf(stderr, "%s(): unsupported cpu!!!\n", __func__); ret_val = OMAPCONF_ERR_CPU; goto mod44xx_get_idle_mode_end; } if (module_id >= OMAP4_MODULE_ID_MAX) { fprintf(stderr, "%s(): incorrect module id!!! (%u)\n", __func__, module_id); ret_val = OMAPCONF_ERR_ARG; goto mod44xx_get_idle_mode_end; } mod44xx_get_interface_type(module_id, &type); if ((module_id != OMAP4_MPU_M3) && (type != MOD_INTERFACE_SLAVE) && (type != MOD_INTERFACE_DUAL)) { dprintf("%s(): module #%d name = %s has no slave interface\n", __func__, module_id, mod44xx_get_name(module_id, name)); ret_val = OMAPCONF_ERR_NOT_AVAILABLE; goto mod44xx_get_idle_mode_end; } ret_val = mod44xx_is_accessible(module_id); if (ret_val == 0) { /* Module is NOT accessible */ ret_val = 0; dprintf("%s(): module #%d name = %s is NOT accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); goto mod44xx_get_idle_mode_end; } else if (ret_val != 1) { /* internal error */ dprintf("%s(): mod44xx_is_accessible() returned with %d!!!\n", __func__, ret_val); goto mod44xx_get_idle_mode_end; } /* Module is accessible */ dprintf("%s(): module #%d name = %s is accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); if ((module_id != OMAP4_MPU_M3) && (mod44xx_info_table[module_id].sysconfig_addr == NULL)) { fprintf(stderr, "%s(): error module %s interface type is not NONE but SYSCONFIG ADDR == NULL\n", __func__, mod44xx_get_name(module_id, name)); ret_val = OMAPCONF_ERR_INTERNAL; goto mod44xx_get_idle_mode_end; } if (module_id != OMAP4_MPU_M3) { OMAP_READREG((unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); dprintf("%s(): SYSCONFIG ADDR = 0x%08X, SYSCONFIG = 0x%08X\n", __func__, (unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); } else { OMAP_READREG((unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG, sysconfig); dprintf( "%s(): SYSCONFIG ADDR = 0x%08X, IDLE_CORE_SYSCONFIG = 0x%08X\n", __func__, (unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG, sysconfig); } /* get module's idle mode */ switch (module_id) { case OMAP4_MCASP: case OMAP4_MPU_M3: *mode = (mod_idle_mode) extract_bitfield(sysconfig, 0, 2); ret_val = 1; dprintf("%s(): module %s idle mode (bits [1:0])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; case OMAP4_CONTROL_GEN_WKUP: case OMAP4_CONTROL_PADCONF_WKUP: case OMAP4_SLIMBUS1: case OMAP4_SLIMBUS2: case OMAP4_IVAHD: case OMAP4_ICONT1: case OMAP4_ICONT2: case OMAP4_VDMA: case OMAP4_IME3: case OMAP4_IPE3: case OMAP4_ILF3: case OMAP4_MC3: case OMAP4_CALC3: case OMAP4_ECD3: case OMAP4_CONTROL_GEN_CORE: case OMAP4_CONTROL_PADCONF_CORE: case OMAP4_SYSTEM_MAILBOX: case OMAP4_DMM: case OMAP4_AESS: case OMAP4_BTE: case OMAP4_CBUFF: case OMAP4_FDIF: case OMAP4_HDMI: case OMAP4_GFX: case OMAP4_MMC1_HL: case OMAP4_MMC2_HL: case OMAP4_MMC3_HL: case OMAP4_MMC4_HL: case OMAP4_MMC5_HL: case OMAP4_UNIPRO1: case OMAP4_FSUSBHOST: case OMAP4_HSUSBHOST: case OMAP4_MCSPI1_HL: case OMAP4_MCSPI2_HL: case OMAP4_MCSPI3_HL: case OMAP4_MCSPI4_HL: case OMAP4_DMIC: case OMAP4_MCPDM: case OMAP4_TIMER1: case OMAP4_TIMER2: case OMAP4_TIMER3: case OMAP4_TIMER4: case OMAP4_TIMER5: case OMAP4_TIMER6: case OMAP4_TIMER7: case OMAP4_TIMER8: case OMAP4_TIMER9: case OMAP4_TIMER10: case OMAP4_TIMER11: case OMAP4_ISS: *mode = (mod_idle_mode) extract_bitfield(sysconfig, 2, 2); ret_val = 1; dprintf("%s(): module %s idle mode (bits [3:2])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; case OMAP4_DSP: case OMAP4_DSP_WUGEN: case OMAP4_TCTRL: case OMAP4_RSZ: case OMAP4_SIMCOP_DCT: case OMAP4_SIMCOP_VLCDJ: case OMAP4_SIMCOP_ROT: case OMAP4_HDQ1W: ret_val = OMAPCONF_ERR_NOT_AVAILABLE; dprintf("%s(): module %s does not have IDLE mode\n", __func__, mod44xx_get_name(module_id, name)); break; case OMAP4_SMARTREFLEX_CORE: case OMAP4_SMARTREFLEX_MPU: case OMAP4_SMARTREFLEX_IVA: *mode = (mod_idle_mode) extract_bitfield(sysconfig, 24, 2); ret_val = 1; dprintf("%s(): module %s idle mode (bits [25:24])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; default: *mode = (mod_idle_mode) extract_bitfield(sysconfig, 3, 2); ret_val = 1; dprintf("%s(): module %s idle mode (bits [4:3])=%d\n", __func__, mod44xx_get_name(module_id, name), *mode); } mod44xx_get_idle_mode_end: return ret_val; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_is_accessible * @BRIEF check omap module's registers accessibility * @RETURNS 1 if omap module's registers accessible * 0 if omap module's registers NOT accessible * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_CPU * @param[in] module_id: omap module ID * @DESCRIPTION check omap module's registers accessibility *//*------------------------------------------------------------------------ */ int mod44xx_is_accessible(mod44xx_id module_id) { unsigned int cm_clkctrl_addr, cm_clkctrl; int ret = 0; mod_module_mode mmode; #ifdef MODULE44XX_DEBUG char name[MOD44XX_MAX_NAME_LENGTH]; #endif if (!cpu_is_omap44xx()) { fprintf(stderr, "%s(): cpu is not omap44xx!!!\n", __func__); ret = OMAPCONF_ERR_CPU; goto mod44xx_is_accessible_exit; } if (module_id >= OMAP4_MODULE_ID_MAX) { fprintf(stderr, "%s(): module_id >= OMAP4_MODULE_ID_MAX!!!\n", __func__); ret = OMAPCONF_ERR_ARG; goto mod44xx_is_accessible_exit; } /* Retrieve module mode */ mod44xx_get_mode(module_id, &mmode); if (mmode == MOD_DISABLED_MODE) { dprintf( "%s(): module #%d name = %s mode is disabled => NOT accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); ret = 0; goto mod44xx_is_accessible_exit; } else if (mmode == MOD_ENABLED_MODE) { dprintf( "%s(): module #%d name = %s mode is enabled => accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); ret = 1; goto mod44xx_is_accessible_exit; } /* Module mode is HW Auto, need to check status */ /* Retrieve CM_CLKCTRL address */ cm_clkctrl_addr = (unsigned int) mod44xx_info_table[module_id].cm_clkctrl_addr; dprintf("%s(): module #%d name = %s CM_CLKCTRL ADDR = 0x%08X\n", __func__, module_id, mod44xx_get_name(module_id, name), cm_clkctrl_addr); /* Retrieve module state */ if ((void *) cm_clkctrl_addr != NULL) { if (mem_read(cm_clkctrl_addr, &cm_clkctrl) != 0) { fprintf(stderr, "%s(): could not read register!!!\n", __func__); ret = OMAPCONF_ERR_REG_ACCESS; goto mod44xx_is_accessible_exit; } dprintf( "%s(): CM_CLKCTRL ADDR = 0x%08X CM_CLKCTRL = 0x%08X IDLEST = %d\n", __func__, (unsigned int) mod44xx_info_table[module_id].cm_clkctrl_addr, cm_clkctrl, extract_bitfield(cm_clkctrl, 16, 2)); /* Check if module is accessible */ switch (extract_bitfield(cm_clkctrl, 16, 2)) { case 0: /* Module is fully functional, including OCP */ dprintf( "%s(): module is fully functional, including OCP\n", __func__); ret = 1; break; case 1: /* * Module is performing transition: wakeup, or sleep, * or sleep abortion */ dprintf( "%s(): module is performing transition: wakeup, or sleep, or sleep abortion\n", __func__); ret = 0; break; case 2: /* Module is in Idle mode (only OCP part) */ dprintf( "%s(): module is in Idle mode (only OCP part)\n", __func__); ret = 0; break; case 3: /* Module is disabled and cannot be accessed */ dprintf( "%s(): module is disabled and cannot be accessed\n", __func__); ret = 0; } } else { /* mod44xx_is_accessible(): * module has NO CM_CLKCTRL, it's always ON */ dprintf("%s(): module has NO CM_CLKCTRL, always ON\n", __func__); ret = 1; } mod44xx_is_accessible_exit: dprintf("%s(%d) = %d\n", __func__, module_id, ret); return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION cpu_detect * @BRIEF Detect cpu and set internal global variables accordingly * @RETURNS 0 on success * OMAPCONF_ERR_UNEXPECTED * OMAPCONF_ERR_CPU if cpu not recognized * OMAPCONF_ERR_REG_ACCESS * @param[in] none * @DESCRIPTION Detect cpu and set internal global variables accordingly *//*------------------------------------------------------------------------ */ int cpu_detect(void) { unsigned int status; unsigned int efuse; unsigned int prod_id_1; int ret; unsigned char status_bit_start; #ifdef CPUID_DEBUG char s[CPU_FULL_NAME_MAX_LENGTH]; char rev_s[CPU_REVISION_MAX_NAME_LENGTH]; char dev_type_s[CPU_DEVICE_TYPE_MAX_NAME_LENGTH]; #endif /* Init variables */ cpu_init(); /* Retrieve OMAP chip & ES */ /* Determine if device is of the AM or OMAP family */ if (cpu_is_omap()) ret = identify_omap(); else ret = identify_sitara(); if (ret) return ret; dprintf("%s(): Chip is %s ES%s\n", __func__, cpu_gets(s), cpu_revision_gets(rev_s)); /* Retrieve device type */ if (cpu_is_omap44xx()) { ret = mem_read(OMAP44XX_STATUS, &status); status_bit_start = 8; } else if (cpu_is_omap54xx() || cpu_is_dra7xx()) { ret = mem_read(OMAP54XX_STATUS, &status); status_bit_start = 6; } else if (cpu_is_am335x() || cpu_is_am437x()) { ret = mem_read(AM335X_STATUS, &status); status_bit_start = 8; } else { ret = -1; } if (ret) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): OMAP44XX_STATUS = 0x%08X\n", __func__, status); switch (extract_bitfield(status, status_bit_start, 2)) { case 3: cpu_device_type_set(DEV_GP); break; case 2: cpu_device_type_set(DEV_HS); break; case 1: cpu_device_type_set(DEV_EMU); break; default: cpu_device_type_set(DEV_TEST); } dprintf("%s(): Device Type is %s\n", __func__, cpu_device_type_gets(dev_type_s)); /* Retrieve silicon performance type from EFuse */ if (cpu_is_omap44xx()) { if (mem_read(CONTROL_STD_FUSE_PROD_ID_1, &prod_id_1) != 0) { fprintf(stderr, "omapconf (%s()): could not read CONTROL_STD_FUSE_PROD_ID_1 register!\n", __func__); return OMAPCONF_ERR_REG_ACCESS; } dprintf("%s(): CONTROL_STD_FUSE_PROD_ID_1 = 0x%08X\n", __func__, prod_id_1); si_type = (silicon_type) extract_bitfield(prod_id_1, 16, 2); } else if (cpu_is_omap54xx()) { if (cpu_revision_get() == REV_ES1_0) { if (cpu_silicon_max_speed_get() != 1200) cpu_silicon_type_set(STANDARD_PERF_SI); else cpu_silicon_type_set(SPEEDBIN_SI); } else { if (cpu_silicon_max_speed_get() != 1700) cpu_silicon_type_set(STANDARD_PERF_SI); else cpu_silicon_type_set(SPEEDBIN_SI); } } else if (cpu_is_dra7xx()) { /* TBD: implement true detection when ID data is available */ cpu_silicon_type_set(STANDARD_PERF_SI); } else if (cpu_is_am335x()){ if (mem_read(EFUSE_SMA_REG, &efuse) != 0) { fprintf(stderr, "omapconf: (%s()): could not read EFUSE_SMA register!\n", __func__); return OMAPCONF_ERR_REG_ACCESS; } switch (extract_bitfield(efuse, 16, 2)) { case 0: /* * Silicon revision 1.0 does not support EFUSE SMA REG * (returns all 0's if read) * Setting as unknown until there is an alternate method */ cpu_package_type_set(PACKAGE_TYPE_MAX); break; case 1: cpu_package_type_set(ZCZ); break; case 2: cpu_package_type_set(ZCE); break; default: fprintf(stderr, "omapconf: (%s()): could not identify package type!\n", __func__); return OMAPCONF_ERR_UNEXPECTED; } } dprintf("%s(): Silicon performance type is %s (%uMHz)\n", __func__, cpu_silicon_type_gets(s), cpu_silicon_max_speed_get()); /* Set CPU full name */ cpu_full_name_set(); dprintf("%s(): CPU full name is %s\n", __func__, cpu_full_name); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION pwrdm44xx_get_state * @BRIEF extract current power domain state from register * @RETURNS 0 on success * OMAPCONF_ERR_ARG * @param[in] pd_id: domain name (MPU, CORE, PER, ...) * @param[in,out] state: current power domain state (returned) * @DESCRIPTION extract current power domain state from register *//*------------------------------------------------------------------------ */ int pwrdm44xx_get_state(pwrdm44xx_id pd_id, pwrdm_state *state) { unsigned int pm_pwrstst_addr, pwrstst; #ifdef PWRDM44XX_DEBUG char pwrdm_name[PWRDM44XX_MAX_NAME_LENGTH]; #endif if (state == NULL) return OMAPCONF_ERR_ARG; /* Retrieve registers address */ switch (pd_id) { case OMAP4_PD_ABE: pm_pwrstst_addr = OMAP4430_PM_ABE_PWRSTST; break; case OMAP4_PD_IVA_HD: pm_pwrstst_addr = OMAP4430_PM_IVAHD_PWRSTST; break; case OMAP4_PD_DSP: pm_pwrstst_addr = OMAP4430_PM_DSP_PWRSTST; break; case OMAP4_PD_CAM: pm_pwrstst_addr = OMAP4430_PM_CAM_PWRSTST; break; case OMAP4_PD_DSS: pm_pwrstst_addr = OMAP4430_PM_DSS_PWRSTST; break; case OMAP4_PD_GFX: pm_pwrstst_addr = OMAP4430_PM_GFX_PWRSTST; break; case OMAP4_PD_WKUP: case OMAP4_PD_EMU: case OMAP4_PD_ALWON_MPU: case OMAP4_PD_STD_EFUSE: case OMAP4_PD_CUST_EFUSE: case OMAP4_PD_ALWON_IVA: case OMAP4_PD_ALWON_CORE: /* ALWAYS ON domains */ *state = PWRDM_ON_STATE; return 0; case OMAP4_PD_MPU: pm_pwrstst_addr = OMAP4430_PM_MPU_PWRSTST; break; case OMAP4_PD_CORE: pm_pwrstst_addr = OMAP4430_PM_CORE_PWRSTST; break; case OMAP4_PD_L3_INIT: pm_pwrstst_addr = OMAP4430_PM_L3INIT_PWRSTST; break; case OMAP4_PD_L4_PER: pm_pwrstst_addr = OMAP4430_PM_L4PER_PWRSTST; break; default: dprintf("pwrdm44xx_get_state(): " "called with incorrect power domain ID (%s)\n", pwrdm44xx_get_name(pd_id, pwrdm_name)); return OMAPCONF_ERR_ARG; } /* Retrieve registers content */ mem_read(pm_pwrstst_addr, &pwrstst); dprintf("pwrdm44xx_get_state(): " "Domain is %s pm_pwrstst_addr = 0x%08X pwrstst = 0x%08X\n", pwrdm44xx_get_name(pd_id, pwrdm_name), pm_pwrstst_addr, pwrstst); /* Retrieve power domain current state */ *state = (pwrdm_state) extract_bitfield(pwrstst, 0, 2); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION twl603x_vsel_get * @BRIEF return vsel-encoded voltage of a given SMPS voltage rail * @RETURNS VSEL-encoded voltage (8-bit, >= 0) in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_INTERNAL * @param[in] vdd_id: voltage domain ID * @DESCRIPTION return vsel-encoded voltage of a given SMPS voltage rail * NB: not supported by TWL6030/TWL6032. *//*------------------------------------------------------------------------ */ int twl603x_vsel_get(unsigned int vdd_id) { int ret; unsigned int val, vsel_addr, vsel, range; const twl6035_smps_registers **vdd_smps_regs; const twl6035_smps_registers *smps_regs; if (!twl603x_is_twl6035()) return OMAPCONF_ERR_CPU; CHECK_ARG_LESS_THAN(vdd_id, 3, OMAPCONF_ERR_ARG); /* Retrive SMPS registers addresses */ vdd_smps_regs = twl6035_smps_vdd54xx[vdd_id]; if (vdd_smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; smps_regs = *vdd_smps_regs; if (smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; dprintf("%s(): vdd_id=%u ADDR: ctrl=0x%02X tstep=0x%02X force=0x%02X " "voltage=0x%02X\n", __func__, vdd_id, smps_regs->ctrl, smps_regs->tstep, smps_regs->force, smps_regs->voltage); /* Check SMPS Status */ /* FIXME: create dedicated API */ if (smps_regs->ctrl == -1) { dprintf("%s(): SMPSxx_CTRL addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } ret = i2cget(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->ctrl, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPSxx_CTRL=0x%02X\n", __func__, val); if (extract_bitfield(val, 4, 2) == 0) { dprintf("(%s(): warning SMPS is OFF\n", __func__); return 0; } /* Check SMPS voltage controlled by registers, not resource pins */ /* FIXME: create dedicated API */ if (extract_bit(val, 6) == 1) { dprintf("%s(): SMPS voltage controlled by resource pins\n", __func__); return OMAPCONF_ERR_NOT_AVAILABLE; } /* * Retrieve if voltage is controlled via * SMPSxx_FORCE.VSEL or SMPSxx_VOLTAGE.VSEL */ if (smps_regs->force == -1) { dprintf("%s(): SMPSxx_FORCE register does not exist, " "use SMPSxx_VOLTAGE register.\n", __func__); vsel_addr = smps_regs->voltage; } else { ret = i2cget(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->force, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPSxx_FORCE=0x%02X\n", __func__, val); if (extract_bit(val, 7) == 1) { dprintf("%s(): CMD=1 => use SMPSxx_VOLTAGE register.\n", __func__); vsel_addr = smps_regs->voltage; } else { dprintf("%s(): CMD=0 => use SMPSxx_FORCE register.\n", __func__); vsel_addr = smps_regs->force; } } /* Retrieve VSEL (7-bit LSB) from relevant register */ if (vsel_addr == (unsigned int) smps_regs->voltage) { if (smps_regs->voltage == -1) { dprintf("%s(): SMPSxx_VOLTAGE addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } ret = i2cget(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->voltage, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPSxx_VOLTAGE=0x%02X\n", __func__, val); } vsel = extract_bitfield(val, 0, 7); dprintf("%s(): SMPSxx_VOLTAGE=0x%02X SMPSxx_VOLTAGE.VSEL=0x%02X\n", __func__, val, vsel); /* Retrieve VSEL range from SMPSxx_VOLTAGE register (bit 7) */ if (vsel_addr != (unsigned int) smps_regs->voltage) { if (smps_regs->voltage == -1) { dprintf("%s(): SMPSxx_VOLTAGE addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } ret = i2cget(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->voltage, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; } range = extract_bit(val, 7); dprintf("%s(): SMPSxx_VOLTAGE=0x%02X SMPSxx_VOLTAGE.RANGE=%u\n", __func__, val, range); /* Return VSEL (7-bit LSB), including range (MSB) */ vsel = vsel | (range << 7); dprintf("%s(): vsel=0x%02X\n", __func__, vsel); return vsel; }
/* ------------------------------------------------------------------------*//** * @FUNCTION tps65217x_vsel_get * @BRIEF return vsel-encoded voltage of a given SMPS voltage rail * @RETURNS VSEL-encoded voltage (8-bit, >= 0) in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_INTERNAL * @param[in] smps_id: voltage domain ID * @DESCRIPTION return vsel-encoded voltage of a given SMPS voltage rail *//*------------------------------------------------------------------------ */ int tps65217x_vsel_get(unsigned int smps_id) { int ret; unsigned int val, vsel, stat_bit; const tps65217x_smps_registers **vdd_smps_regs; const tps65217x_smps_registers *smps_regs; CHECK_ARG_LESS_THAN(smps_id, 5, OMAPCONF_ERR_ARG); /* Retrive SMPS registers addresses */ vdd_smps_regs = tps65217x_smps_vdd_am335x[smps_id]; if (vdd_smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; smps_regs = *vdd_smps_regs; if (smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; dprintf("%s(): smps_id=%u ADDR: ctrl=0x%02X tstep=0x%02X " "voltage=0x%02X\n", __func__, smps_id, smps_regs->ctrl, smps_regs->tstep, smps_regs->voltage); /* Check SMPS Status */ if (smps_regs->ctrl == -1) { dprintf("%s(): SMPSxx_CTRL addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } ret = i2cget(TPS65217X_I2C_BUS, TPS65217X_ID0_ADDR, smps_regs->ctrl, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; /* MPU and CORE share same enable register */ switch (chip_type) { case 6: /* * TPS65217A is for AM335X ZCE package * MPU and CORE are combined for this package */ stat_bit = 3; break; case 7: if (smps_id == 0) stat_bit = 4; else stat_bit = 3; break; case 8: case 9: if (smps_id == 0) stat_bit = 3; else stat_bit = 4; break; default: fprintf(stderr, "%s(): should not reach here?!\n", __func__); return OMAPCONF_ERR_INTERNAL; } dprintf("%s(): SMPSxx_CTRL=0x%02X\n", __func__, val); if (extract_bit(val, stat_bit) == 0) { dprintf("(%s(): warning SMPS is OFF\n", __func__); return 0; } /* Check SMPS voltage controlled by registers, not resource pins */ ret = i2cget(TPS65217X_I2C_BUS, TPS65217X_ID0_ADDR, smps_regs->voltage, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; if (extract_bit(val, 7) == 1) { dprintf("%s(): SMPS voltage controlled by resource pins\n", __func__); return OMAPCONF_ERR_NOT_AVAILABLE; } /* Retrieve VSEL (6-bits) from relevant register */ if (smps_regs->voltage != -1) { ret = i2cget(TPS65217X_I2C_BUS, TPS65217X_ID0_ADDR, smps_regs->voltage, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPSxx_VOLTAGE=0x%02X\n", __func__, val); } else { dprintf("%s(): SMPSxx_VOLTAGE addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } vsel = extract_bitfield(val, 0, TPS65217X_VSEL_LEN); dprintf("%s(): SMPSxx_VOLTAGE=0x%02X SMPSxx_VOLTAGE.VSEL=0x%02X\n", __func__, val, vsel); return vsel; }
/* ------------------------------------------------------------------------*//** * @FUNCTION twl603x_uvoltage_set * @BRIEF set voltage of a given SMPS voltage rail. * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_INTERNAL * @param[in] vdd_id: voltage domain ID * @param[in] uv: voltage to be set (in micro-volt) * @DESCRIPTION set voltage of a given SMPS voltage rail, in micro-volt. * NB: not supported by TWL6030/TWL6032. *//*------------------------------------------------------------------------ */ int twl603x_uvoltage_set(unsigned int vdd_id, unsigned long uv) { int ret; unsigned int val; unsigned char vsel; const twl6035_smps_registers **vdd_smps_regs; const twl6035_smps_registers *smps_regs; if (!twl603x_is_twl6035()) return OMAPCONF_ERR_CPU; CHECK_ARG_LESS_THAN(vdd_id, 3, OMAPCONF_ERR_ARG); /* Retrive SMPS registers addresses */ vdd_smps_regs = twl6035_smps_vdd54xx[vdd_id]; if (vdd_smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; smps_regs = *vdd_smps_regs; if (smps_regs == NULL) return OMAPCONF_ERR_INTERNAL; dprintf("%s(): vdd_id=%u ADDR: ctrl=0x%02X tstep=0x%02X force=0x%02X " "voltage=0x%02X\n", __func__, vdd_id, smps_regs->ctrl, smps_regs->tstep, smps_regs->force, smps_regs->voltage); /* Check SMPS Status */ /* FIXME: create dedicated API */ if (smps_regs->ctrl == -1) { dprintf("%s(): SMPSxx_CTRL addr=-1!!!\n", __func__); return OMAPCONF_ERR_INTERNAL; } ret = i2cget(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->ctrl, &val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPSxx_CTRL=0x%02X\n", __func__, val); if (extract_bitfield(val, 4, 2) == 0) { dprintf("(%s(): SMPS is OFF\n", __func__); return OMAPCONF_ERR_NOT_AVAILABLE; } /* Make sure SMPSxx_CTRL.ROOF_FLOOR_EN=0 */ /* FIXME: create dedicated API */ if (extract_bit(val, 6) == 1) { dprintf("%s(): SMPS voltage controlled by resource pins, " "clearing ROOF_FLOOR_EN bit.\n", __func__); /* Clear ROOF_FLOOR_EN bit (6) */ val = val & 0xBF; ret = i2cset(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->ctrl, (unsigned int) val); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): SMPS voltage now controlled by " "SMPS12_FORCE.CMD bit.\n", __func__); } else { dprintf("%s(): SMPS voltage controlled by " "SMPS12_FORCE.CMD bit.\n", __func__); } /* Convert voltage to VSEL */ vsel = twl603x_uv_to_vsel(vdd_id, uv); dprintf("%s(): uv=%lu vsel=0x%02X\n", __func__, uv, vsel); /* Write VSEL to SMPSxx_VOLTAGE */ ret = i2cset(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->voltage, (unsigned int) vsel); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; /* * Try to switch voltage control to SMPSxx_FORCE register (if exists) * so that voltage will not be overriden by kernel during * DVFS, AVS or power transition. */ if (smps_regs->force != -1) { dprintf("%s(): SMPSxx_FORCE exists, switching control.\n", __func__); /* Clear bit 7 (CMD) */ val = vsel & 0x7F; ret = i2cset(TWL6035_I2C_BUS, TWL6035_ID1_ADDR, smps_regs->force, (unsigned int) val); } else { dprintf("%s(): SMPSxx_FORCE does not exist.\n", __func__); ret = 0; } return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION cpu_detect * @BRIEF Detect cpu and set internal global variables accordingly * @RETURNS 0 on success * OMAPCONF_ERR_UNEXPECTED * OMAPCONF_ERR_CPU if cpu not recognized * OMAPCONF_ERR_REG_ACCESS * @param[in] none * @DESCRIPTION Detect cpu and set internal global variables accordingly *//*------------------------------------------------------------------------ */ int cpu_detect(void) { unsigned int id_code; unsigned int status; unsigned int prod_id_1; #ifdef CPUID_DEBUG char s[CPU_FULL_NAME_MAX_LENGTH]; char rev_s[CPU_REVISION_MAX_NAME_LENGTH]; char dev_type_s[CPU_DEVICE_TYPE_MAX_NAME_LENGTH]; #endif /* Init variables */ cpu_init(); /* Retrieve OMAP chip & ES */ if (mem_read(ID_CODE, &id_code) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): ID_CODE = 0x%08X\n", __func__, id_code); switch (id_code) { case OMAP5432_ES_1_0_ID_CODE: cpu_set(OMAP_5432); cpu_revision_set(REV_ES1_0); break; case OMAP5430_ES_1_0_ID_CODE: case 0x0000002F: /* Zebu */ cpu_set(OMAP_5430); cpu_revision_set(REV_ES1_0); break; case OMAP4470_ES_1_0_ID_CODE: cpu_set(OMAP_4470); cpu_revision_set(REV_ES1_0); break; case OMAP4460_ES_1_1_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_1); break; case OMAP4460_ES_1_0_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_0); break; case OMAP4430_ES_2_3_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_3); break; case OMAP4430_ES_2_2_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_2); break; case OMAP4430_ES_2_1_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_1); break; case OMAP4430_ES_2_0_ID_CODE: case OMAP4430_ES_1_0_ID_CODE: /* * Due to fusing issue between ES1.0 and ES2.0 (same code...), * revision cannot be correctly detected. * Workaround is to use Cortex-A9 own revision code, which did * changed, but it is not accessible from user space... * Only way is to use /proc/cpuinfo. */ cpu_set(OMAP_4430); cpu_rev_get_from_cpuinfo(&cpu_rev); switch (cpu_rev) { case REV_ES2_0: cpu_revision_set(REV_ES2_0); break; case REV_ES1_0: cpu_revision_set(REV_ES1_0); break; default: dprintf("%s(): unknown ARM Cortex-A9!\n", __func__); return OMAPCONF_ERR_UNEXPECTED; } break; default: dprintf("%s(): OMAP ID CODE not recognized! (0x%08X)\n", __func__, id_code); return OMAPCONF_ERR_CPU; } dprintf("%s(): Chip is %s ES%s\n", __func__, cpu_gets(s), cpu_revision_gets(rev_s)); /* Retrieve device type */ if (mem_read(OMAP44XX_STATUS, &status) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): OMAP44XX_STATUS = 0x%08X\n", __func__, status); switch (extract_bitfield(status, 8, 2)) { case 3: cpu_device_type_set(DEV_GP); break; case 2: cpu_device_type_set(DEV_HS); break; case 1: cpu_device_type_set(DEV_EMU); break; default: cpu_device_type_set(DEV_TEST); } dprintf("%s(): Device Type is %s\n", __func__, cpu_device_type_gets(dev_type_s)); /* Retrieve silicon performance type from EFuse */ if (mem_read(CONTROL_STD_FUSE_PROD_ID_1, &prod_id_1) != 0) { fprintf(stderr, "omapconf (%s()): could not read CONTROL_STD_FUSE_PROD_ID_1 register!\n", __func__); return OMAPCONF_ERR_REG_ACCESS; } dprintf("%s(): CONTROL_STD_FUSE_PROD_ID_1 = 0x%08X\n", __func__, prod_id_1); si_type = (silicon_type) extract_bitfield(prod_id_1, 16, 2); dprintf("%s(): Silicon performance type is %s (%uMHz)\n", __func__, cpu_silicon_type_gets(s), cpu_silicon_max_speed_get()); /* Set CPU full name */ cpu_full_name_set(); dprintf("%s(): CPU full name is %s\n", __func__, cpu_full_name); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mod44xx_get_clock_activity_mode * @BRIEF retrieve omap module's clockactivity mode * @RETURNS 1 if success * 0 if omap module's registers NOT accessible * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_CPU * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_INTERNAL * @param[in] module_id: omap module ID * @param[in,out] mode: returned omap module's clockactivity mode * @DESCRIPTION retrieve omap module's clockactivity mode *//*------------------------------------------------------------------------ */ int mod44xx_get_clock_activity_mode(mod44xx_id module_id, mod_clock_activity_mode *mode) { int ret_val = 0; unsigned int sysconfig; char name[MOD44XX_MAX_NAME_LENGTH]; *mode = MOD_CLOCK_ACTIVITY_MODE_MAX; if (!cpu_is_omap44xx()) return OMAPCONF_ERR_CPU; if (module_id >= OMAP4_MODULE_ID_MAX) return OMAPCONF_ERR_ARG; if (mod44xx_has_clockactivity_bit(module_id) != 1) return OMAPCONF_ERR_NOT_AVAILABLE; ret_val = mod44xx_is_accessible(module_id); if (ret_val == 1) { /* Module is accessible */ dprintf("%s(): module #%d name = %s is accessible\n", __func__, module_id, mod44xx_get_name(module_id, name)); if (mod44xx_info_table[module_id].sysconfig_addr != NULL) { OMAP_READREG((unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); dprintf( "%s(): SYSCONFIG ADDR = 0x%08X SYSCONFIG = 0x%08X\n", __func__, (unsigned int) mod44xx_info_table[module_id].sysconfig_addr, sysconfig); /* Check module's idle mode */ switch (module_id) { case OMAP4_SPINLOCK: case OMAP4_ELM: *mode = (mod_clock_activity_mode) extract_bit(sysconfig, 8); ret_val = 1; dprintf( "%s(): module %s clockactivity bit 8 = %d\n", __func__, mod44xx_get_name(module_id, name), *mode); break; default: *mode = (mod_clock_activity_mode) extract_bitfield(sysconfig, 8, 2); ret_val = 1; dprintf( "%s(): module %s clockactivity (bits [9:8]) = %d\n", __func__, mod44xx_get_name(module_id, name), *mode); } } else { fprintf(stderr, "%s(): error module's %s interface type is not NONE but SYSCONFIG ADDR == NULL\n", __func__, mod44xx_get_name(module_id, name)); ret_val = OMAPCONF_ERR_INTERNAL; } } else if (ret_val == 0) { /* Module is NOT accessible */ ret_val = 0; dprintf("%s(): module is NOT accessible\n", __func__); } else { /* internal error */ dprintf("%s(): mod44xx_is_accessible() returned with %d\n", __func__, ret_val); } return ret_val; }