static void exynos4_cpu_prepare(void)
{
void __iomem *inform0, *inform1;
if (trustzone_on()) {
inform0 = S5P_VA_SYSRAM_NS + 0x8;
inform1 = S5P_VA_SYSRAM_NS + 0xC;
} else {
inform0 = S5P_INFORM0;
inform1 = S5P_INFORM1;
}
if (exynos4_sleep_gpio_set)
exynos4_sleep_gpio_set();
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, inform1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), inform0);
/* Before enter central sequence mode, clock src register have to set */
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
static void exynos4_cpu_prepare(void)
{
if (exynos4_sleep_gpio_table_set)
exynos4_sleep_gpio_table_set();
/* Set value of power down register for sleep mode */
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
/* Before enter central sequence mode, clock src register have to set */
#ifdef CONFIG_CACHE_L2X0
/* Disable the full line of zero */
disable_cache_foz();
#endif
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
if (soc_is_exynos4210())
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
}
