void __init exynos5_universal5410_power_init(void)
{
exynos5_hs_i2c1_set_platdata(&hs_i2c1_data);
i2c_register_board_info(5, hs_i2c_devs0, ARRAY_SIZE(hs_i2c_devs0));
#ifdef CONFIG_PM_DEVFREQ
s3c_set_platdata(&universal5410_qos_mif_pd, sizeof(struct exynos_devfreq_platdata),
&exynos5_mif_devfreq);
s3c_set_platdata(&universal5410_qos_int_pd, sizeof(struct exynos_devfreq_platdata),
&exynos5_int_devfreq);
#endif
s3c_set_platdata(&exynos5_tmu_data, sizeof(struct exynos_tmu_platform_data),
&exynos5410_device_tmu);
platform_add_devices(universal5410_power_devices,
ARRAY_SIZE(universal5410_power_devices));
#ifdef CONFIG_SEC_PM
sec_gpio_init();
sec_config_gpio_table();
exynos_set_sleep_gpio_table = sec_config_sleep_gpio_table;
exynos_debug_show_gpio = sec_debug_show_gpio;
#endif
}
void __init exynos5_smdk5410_media_init(void)
{
#if defined (CONFIG_CSI_D) || defined (CONFIG_S5K6B2_CSI_D)
exynos5_hs_i2c1_set_platdata(NULL);
#endif
#if defined (CONFIG_CSI_E) || defined (CONFIG_S5K6B2_CSI_E)
exynos5_hs_i2c2_set_platdata(NULL);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MFC
s5p_mfc_set_platdata(&smdk5410_mfc_pd);
dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
#endif
platform_add_devices(smdk5410_media_devices,
ARRAY_SIZE(smdk5410_media_devices));
#ifdef CONFIG_VIDEO_S5K6B2
#if defined(CONFIG_S5K6B2_CSI_C)
__set_mipi_csi_config(&s5p_mipi_csis0_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_D)
__set_mipi_csi_config(&s5p_mipi_csis1_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_E)
__set_mipi_csi_config(&s5p_mipi_csis2_default_data, s5k6b2.csi_data_align);
#endif
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
s3c_set_platdata(&s5p_mipi_csis0_default_data,
sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
s3c_set_platdata(&s5p_mipi_csis1_default_data,
sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
s3c_set_platdata(&s5p_mipi_csis2_default_data,
sizeof(s5p_mipi_csis2_default_data), &s5p_device_mipi_csis2);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
smdk5410_camera_gpio_cfg();
smdk5410_set_camera_platdata();
s3c_set_platdata(&exynos_flite0_default_data,
sizeof(exynos_flite0_default_data), &exynos_device_flite0);
s3c_set_platdata(&exynos_flite1_default_data,
sizeof(exynos_flite1_default_data), &exynos_device_flite1);
s3c_set_platdata(&exynos_flite2_default_data,
sizeof(exynos_flite2_default_data), &exynos_device_flite2);
#endif
#if defined(CONFIG_VIDEO_EXYNOS_TV)
dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
mxr_platdata.ip_ver = IP_VER_TV_5A_1;
hdmi_platdata.ip_ver = IP_VER_TV_5A_1;
s5p_tv_setup();
/* Below should be enabled after power domain is available */
#if 0
s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
#endif
#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
#endif
s3c_set_platdata(&mxr_platdata, sizeof(mxr_platdata), &s5p_device_mixer);
s5p_hdmi_set_platdata(&hdmi_platdata);
s3c_i2c2_set_platdata(NULL);
i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
#endif
#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
exynos5_gsc_set_ip_ver(IP_VER_GSC_5A);
s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data),
&exynos5_device_gsc0);
s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data),
&exynos5_device_gsc1);
s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data),
&exynos5_device_gsc2);
s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data),
&exynos5_device_gsc3);
#endif
#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
clk_add_alias("gscl_wrap0", FIMC_IS_MODULE_NAME, "gscl_wrap0", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
clk_add_alias("gscl_wrap1", FIMC_IS_MODULE_NAME, "gscl_wrap1", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.2");
clk_add_alias("gscl_wrap2", FIMC_IS_MODULE_NAME, "gscl_wrap2", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, FIMC_IS_MODULE_NAME);
exynos5_fimc_is_data.gpio_info = &gpio_smdk5410;
exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);
if (!exynos_spi_cfg_cs(spi3_csi[0].line, 3)) {
s3c64xx_spi3_set_platdata(&s3c64xx_spi3_pdata,
EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi3_csi));
spi_register_board_info(spi3_board_info,
ARRAY_SIZE(spi3_board_info));
} else {
pr_err("%s: Error requesting gpio for SPI-CH1 CS\n", __func__);
}
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMG2D
s5p_fimg2d_set_platdata(&fimg2d_data);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG
exynos5_jpeg_fimp_setup_clock(&s5p_device_jpeg.dev, 166500000);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG_HX
exynos5_jpeg_hx_setup_clock(&exynos5_device_jpeg_hx.dev, 300000000);
#endif
}
