static void pcap_isr_work(struct work_struct *work) { struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work); struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev); u32 msr, isr, int_sel, service; int irq; do { ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); /* We can't service/ack irqs that are assigned to port 2 */ if (!(pdata->config & PCAP_SECOND_PORT)) { ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); isr &= ~int_sel; } ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); ezx_pcap_write(pcap, PCAP_REG_ISR, isr); local_irq_disable(); service = isr & ~msr; for (irq = pcap->irq_base; service; service >>= 1, irq++) { if (service & 1) generic_handle_irq(irq); } local_irq_enable(); ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); } while (gpio_get_value(pdata->gpio)); }
static void pcap_adc_trigger(struct pcap_chip *pcap) { u32 tmp; u8 head; mutex_lock(&pcap->adc_mutex); head = pcap->adc_head; if (!pcap->adc_queue[head]) { /* queue is empty, save power */ pcap_disable_adc(pcap); mutex_unlock(&pcap->adc_mutex); return; } /* start conversion on requested bank, save TS_M bits */ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) tmp |= PCAP_ADC_AD_SEL1; ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); mutex_unlock(&pcap->adc_mutex); ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); }
static void pcap_adc_trigger(struct pcap_chip *pcap) { u32 tmp; u8 head; mutex_lock(&pcap->adc_mutex); head = pcap->adc_head; if (!pcap->adc_queue[head]) { pcap_disable_adc(pcap); mutex_unlock(&pcap->adc_mutex); return; } ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) tmp |= PCAP_ADC_AD_SEL1; ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); mutex_unlock(&pcap->adc_mutex); ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); }
static int pcap_rtc_set_mmss(struct device *dev, unsigned long secs) { struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev); u32 tod, days; tod = secs % SEC_PER_DAY; ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_TOD, tod); days = secs / SEC_PER_DAY; ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_DAY, days); return 0; }
static void pcap_disable_adc(struct pcap_chip *pcap) { u32 tmp; ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY); ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); }
static int pcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) { struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev); struct rtc_time *tm = &alrm->time; unsigned long secs; u32 tod, days; rtc_tm_to_time(tm, &secs); tod = secs % SEC_PER_DAY; ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_TODA, tod); days = secs / SEC_PER_DAY; ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_DAYA, days); return 0; }
/* ADC */ void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits) { u32 tmp; mutex_lock(&pcap->adc_mutex); ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); mutex_unlock(&pcap->adc_mutex); }
static void pcap_isr_work(struct work_struct *work) { struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work); struct pcap_platform_data *pdata = pcap->spi->dev.platform_data; u32 msr, isr, int_sel, service; int irq; do { ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); /* We cant service/ack irqs that are assigned to port 2 */ if (!(pdata->config & PCAP_SECOND_PORT)) { ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); isr &= ~int_sel; } ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); ezx_pcap_write(pcap, PCAP_REG_ISR, isr); local_irq_disable(); service = isr & ~msr; for (irq = pcap->irq_base; service; service >>= 1, irq++) { if (service & 1) { struct irq_desc *desc = irq_to_desc(irq); if (WARN(!desc, KERN_WARNING "Invalid PCAP IRQ %d\n", irq)) break; if (desc->status & IRQ_DISABLED) note_interrupt(irq, desc, IRQ_NONE); else desc->handle_irq(irq, desc); } } local_irq_enable(); ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); } while (gpio_get_value(irq_to_gpio(pcap->spi->irq))); }
static irqreturn_t pcap_adc_irq(int irq, void *_pcap) { struct pcap_chip *pcap = _pcap; struct pcap_adc_request *req; u16 res[2]; u32 tmp; mutex_lock(&pcap->adc_mutex); req = pcap->adc_queue[pcap->adc_head]; if (WARN(!req, "adc irq without pending request\n")) { mutex_unlock(&pcap->adc_mutex); return IRQ_HANDLED; } /* read requested channels results */ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; pcap->adc_queue[pcap->adc_head] = NULL; pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1); mutex_unlock(&pcap->adc_mutex); /* pass the results and release memory */ req->callback(req->data, res); kfree(req); /* trigger next conversion (if any) on queue */ pcap_adc_trigger(pcap); return IRQ_HANDLED; }
static irqreturn_t pcap_adc_irq(int irq, void *_pcap) { struct pcap_chip *pcap = _pcap; struct pcap_adc_request *req; u16 res[2]; u32 tmp; mutex_lock(&pcap->adc_mutex); req = pcap->adc_queue[pcap->adc_head]; if (WARN(!req, KERN_WARNING "adc irq without pending request\n")) { mutex_unlock(&pcap->adc_mutex); return IRQ_HANDLED; } ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; pcap->adc_queue[pcap->adc_head] = NULL; pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1); mutex_unlock(&pcap->adc_mutex); req->callback(req->data, res); kfree(req); pcap_adc_trigger(pcap); return IRQ_HANDLED; }
static int ezx_pcap_probe(struct spi_device *spi) { struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev); struct pcap_chip *pcap; int i, adc_irq; int ret = -ENODEV; /* platform data is required */ if (!pdata) goto ret; pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL); if (!pcap) { ret = -ENOMEM; goto ret; } mutex_init(&pcap->io_mutex); mutex_init(&pcap->adc_mutex); INIT_WORK(&pcap->isr_work, pcap_isr_work); INIT_WORK(&pcap->msr_work, pcap_msr_work); spi_set_drvdata(spi, pcap); /* setup spi */ spi->bits_per_word = 32; spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); ret = spi_setup(spi); if (ret) goto ret; pcap->spi = spi; /* setup irq */ pcap->irq_base = pdata->irq_base; pcap->workqueue = create_singlethread_workqueue("pcapd"); if (!pcap->workqueue) { ret = -ENOMEM; dev_err(&spi->dev, "can't create pcap thread\n"); goto ret; } /* redirect interrupts to AP, except adcdone2 */ if (!(pdata->config & PCAP_SECOND_PORT)) ezx_pcap_write(pcap, PCAP_REG_INT_SEL, (1 << PCAP_IRQ_ADCDONE2)); /* setup irq chip */ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); irq_set_chip_data(i, pcap); #ifdef CONFIG_ARM set_irq_flags(i, IRQF_VALID); #else irq_set_noprobe(i); #endif } /* mask/ack all PCAP interrupts */ ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); pcap->msr = PCAP_MASK_ALL_INTERRUPT; irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); irq_set_handler_data(spi->irq, pcap); irq_set_chained_handler(spi->irq, pcap_irq_handler); irq_set_irq_wake(spi->irq, 1); /* ADC */ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC", pcap); if (ret) goto free_irqchip; /* setup subdevs */ for (i = 0; i < pdata->num_subdevs; i++) { ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); if (ret) goto remove_subdevs; } /* board specific quirks */ if (pdata->init) pdata->init(pcap); return 0; remove_subdevs: device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); free_irqchip: for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) irq_set_chip_and_handler(i, NULL, NULL); /* destroy_workqueue: */ destroy_workqueue(pcap->workqueue); ret: return ret; }
static void pcap_msr_work(struct work_struct *work) { struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work); ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); }
static int __devinit ezx_pcap_probe(struct spi_device *spi) { struct pcap_platform_data *pdata = spi->dev.platform_data; struct pcap_chip *pcap; int i, adc_irq; int ret = -ENODEV; if (!pdata) goto ret; pcap = kzalloc(sizeof(*pcap), GFP_KERNEL); if (!pcap) { ret = -ENOMEM; goto ret; } mutex_init(&pcap->io_mutex); mutex_init(&pcap->adc_mutex); INIT_WORK(&pcap->isr_work, pcap_isr_work); INIT_WORK(&pcap->msr_work, pcap_msr_work); dev_set_drvdata(&spi->dev, pcap); spi->bits_per_word = 32; spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); ret = spi_setup(spi); if (ret) goto free_pcap; pcap->spi = spi; pcap->irq_base = pdata->irq_base; pcap->workqueue = create_singlethread_workqueue("pcapd"); if (!pcap->workqueue) { dev_err(&spi->dev, "cant create pcap thread\n"); goto free_pcap; } if (!(pdata->config & PCAP_SECOND_PORT)) ezx_pcap_write(pcap, PCAP_REG_INT_SEL, (1 << PCAP_IRQ_ADCDONE2)); for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); set_irq_chip_data(i, pcap); #ifdef CONFIG_ARM set_irq_flags(i, IRQF_VALID); #else set_irq_noprobe(i); #endif } ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); pcap->msr = PCAP_MASK_ALL_INTERRUPT; set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); set_irq_data(spi->irq, pcap); set_irq_chained_handler(spi->irq, pcap_irq_handler); set_irq_wake(spi->irq, 1); adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap); if (ret) goto free_irqchip; for (i = 0; i < pdata->num_subdevs; i++) { ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); if (ret) goto remove_subdevs; } if (pdata->init) pdata->init(pcap); return 0; remove_subdevs: device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); free_irq(adc_irq, pcap); free_irqchip: for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) set_irq_chip_and_handler(i, NULL, NULL); destroy_workqueue(pcap->workqueue); free_pcap: kfree(pcap); ret: return ret; }