static void
emit_gmem2mem_surf(struct fd_context *ctx,
uint32_t base, struct pipe_surface *psurf)
{
struct fd_ringbuffer *ring = ctx->ring;
struct fd_resource *rsc = fd_resource(psurf->texture);
struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf->format)) |
A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf->format)));
fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
}
void
fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
{
int32_t i, j, last = -1;
uint32_t total_in = 0;
const struct fd_vertex_state *vtx = emit->vtx;
struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
unsigned vertex_regid = regid(63, 0), instance_regid = regid(63, 0);
for (i = 0; i < vp->inputs_count; i++) {
uint8_t semantic = sem2name(vp->inputs[i].semantic);
if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
vertex_regid = vp->inputs[i].regid;
else if (semantic == TGSI_SEMANTIC_INSTANCEID)
instance_regid = vp->inputs[i].regid;
else if ((i < vtx->vtx->num_elements) && vp->inputs[i].compmask)
last = i;
}
/* hw doesn't like to be configured for zero vbo's, it seems: */
if ((vtx->vtx->num_elements == 0) &&
(vertex_regid == regid(63, 0)) &&
(instance_regid == regid(63, 0)))
return;
for (i = 0, j = 0; i <= last; i++) {
assert(sem2name(vp->inputs[i].semantic) == 0);
if (vp->inputs[i].compmask) {
struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
const struct pipe_vertex_buffer *vb =
&vtx->vertexbuf.vb[elem->vertex_buffer_index];
struct fd_resource *rsc = fd_resource(vb->buffer);
enum pipe_format pfmt = elem->src_format;
enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
bool switchnext = (i != last) ||
(vertex_regid != regid(63, 0)) ||
(instance_regid != regid(63, 0));
bool isint = util_format_is_pure_integer(pfmt);
uint32_t fs = util_format_get_blocksize(pfmt);
uint32_t off = vb->buffer_offset + elem->src_offset;
uint32_t size = fd_bo_size(rsc->bo) - off;
debug_assert(fmt != ~0);
OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
OUT_RELOC(ring, rsc->bo, off, 0, 0);
OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
total_in += vp->inputs[i].ncomp;
j++;
}
}
OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
0xa0000 | /* XXX */
A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(regid(63, 0)));
OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
/* cache invalidate, otherwise vertex fetch could see
* stale vbo contents:
*/
OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000012);
}
static void
emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
struct pipe_surface **bufs, uint32_t *bases,
uint32_t bin_w, bool decode_srgb)
{
enum a4xx_tile_mode tile_mode;
unsigned i;
if (bin_w) {
tile_mode = 2;
} else {
tile_mode = TILE4_LINEAR;
}
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
enum a4xx_color_fmt format = 0;
enum a3xx_color_swap swap = WZYX;
bool srgb = false;
struct fd_resource *rsc = NULL;
struct fd_resource_slice *slice = NULL;
uint32_t stride = 0;
uint32_t base = 0;
uint32_t offset = 0;
if ((i < nr_bufs) && bufs[i]) {
struct pipe_surface *psurf = bufs[i];
enum pipe_format pformat = psurf->format;
rsc = fd_resource(psurf->texture);
/* In case we're drawing to Z32F_S8, the "color" actually goes to
* the stencil
*/
if (rsc->stencil) {
rsc = rsc->stencil;
pformat = rsc->base.b.format;
bases++;
}
slice = fd_resource_slice(rsc, psurf->u.tex.level);
format = fd4_pipe2color(pformat);
swap = fd4_pipe2swap(pformat);
if (decode_srgb)
srgb = util_format_is_srgb(pformat);
else
pformat = util_format_linear(pformat);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
if (bin_w) {
stride = bin_w * rsc->cpp;
if (bases) {
base = bases[i];
}
} else {
stride = slice->pitch * rsc->cpp;
}
} else if ((i < nr_bufs) && bases) {
base = bases[i];
}
OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
if (bin_w || (i >= nr_bufs) || !bufs[i]) {
OUT_RING(ring, base);
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
} else {
OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
/* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
* not sure if we need to skip it for bypass or
* not.
*/
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
}
}
}
static void
emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
{
enum a4xx_tile_mode tile_mode;
unsigned i;
if (bin_w) {
tile_mode = 2;
} else {
tile_mode = TILE4_LINEAR;
}
for (i = 0; i < 8; i++) {
enum a4xx_color_fmt format = 0;
enum a3xx_color_swap swap = WZYX;
struct fd_resource *rsc = NULL;
struct fd_resource_slice *slice = NULL;
uint32_t stride = 0;
uint32_t base = 0;
uint32_t offset = 0;
if ((i < nr_bufs) && bufs[i]) {
struct pipe_surface *psurf = bufs[i];
rsc = fd_resource(psurf->texture);
slice = fd_resource_slice(rsc, psurf->u.tex.level);
format = fd4_pipe2color(psurf->format);
swap = fd4_pipe2swap(psurf->format);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
if (bin_w) {
stride = bin_w * rsc->cpp;
if (bases) {
base = bases[i];
}
} else {
stride = slice->pitch * rsc->cpp;
}
}
OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
if (bin_w || (i >= nr_bufs)) {
OUT_RING(ring, base);
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
} else {
OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
/* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
* not sure if we need to skip it for bypass or
* not.
*/
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
}
}
}
