static void init(void)
{
int fd = drmOpen("kgsl", NULL);
drmSetMaster(fd);
dev = fd_device_new(fd);
pipe = fd_pipe_new(dev, FD_PIPE_2D);
context_bos[0] = fd_bo_new(dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM);
context_bos[1] = fd_bo_new(dev, 0x9000, DRM_FREEDRENO_GEM_TYPE_KMEM);
context_bos[2] = fd_bo_new(dev, 0x81000, DRM_FREEDRENO_GEM_TYPE_KMEM);
next_ring();
ring_pre(ring);
BEGIN_RING(8);
OUT_RING (ring, REGM(VGV1_DIRTYBASE, 3));
OUT_RELOC (ring, context_bos[0]); /* VGV1_DIRTYBASE */
OUT_RELOC (ring, context_bos[1]); /* VGV1_CBASE1 */
OUT_RELOC (ring, context_bos[2]); /* VGV1_UBASE2 */
OUT_RING (ring, 0x11000000);
OUT_RING (ring, 0x10fff000);
OUT_RING (ring, 0x10ffffff);
OUT_RING (ring, 0x0d000404);
END_RING ();
}
struct pipe_context *
fd4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd4_context *fd4_ctx = CALLOC_STRUCT(fd4_context);
struct pipe_context *pctx;
if (!fd4_ctx)
return NULL;
pctx = &fd4_ctx->base.base;
fd4_ctx->base.dev = fd_device_ref(screen->dev);
fd4_ctx->base.screen = fd_screen(pscreen);
pctx->destroy = fd4_context_destroy;
pctx->create_blend_state = fd4_blend_state_create;
pctx->create_rasterizer_state = fd4_rasterizer_state_create;
pctx->create_depth_stencil_alpha_state = fd4_zsa_state_create;
fd4_draw_init(pctx);
fd4_gmem_init(pctx);
fd4_texture_init(pctx);
fd4_prog_init(pctx);
fd4_emit_init(pctx);
pctx = fd_context_init(&fd4_ctx->base, pscreen, primtypes, priv);
if (!pctx)
return NULL;
util_dynarray_init(&fd4_ctx->rbrc_patches);
fd4_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd4_ctx->fs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd4_ctx->vsc_size_mem = fd_bo_new(screen->dev, 0x1000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd4_ctx->solid_vbuf = create_solid_vertexbuf(pctx);
fd4_ctx->blit_texcoord_vbuf = create_blit_texcoord_vertexbuf(pctx);
/* setup solid_vbuf_state: */
fd4_ctx->solid_vbuf_state.vtx = pctx->create_vertex_elements_state(
pctx, 1, (struct pipe_vertex_element[]){{
.vertex_buffer_index = 0,
.src_offset = 0,
.src_format = PIPE_FORMAT_R32G32B32_FLOAT,
}});
struct pipe_context *
fd4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd4_context *fd4_ctx = CALLOC_STRUCT(fd4_context);
struct pipe_context *pctx;
if (!fd4_ctx)
return NULL;
pctx = &fd4_ctx->base.base;
pctx->screen = pscreen;
fd4_ctx->base.dev = fd_device_ref(screen->dev);
fd4_ctx->base.screen = fd_screen(pscreen);
pctx->destroy = fd4_context_destroy;
pctx->create_blend_state = fd4_blend_state_create;
pctx->create_rasterizer_state = fd4_rasterizer_state_create;
pctx->create_depth_stencil_alpha_state = fd4_zsa_state_create;
fd4_draw_init(pctx);
fd4_gmem_init(pctx);
fd4_texture_init(pctx);
fd4_prog_init(pctx);
fd4_emit_init(pctx);
pctx = fd_context_init(&fd4_ctx->base, pscreen, primtypes, priv, flags);
if (!pctx)
return NULL;
fd_hw_query_init(pctx);
fd4_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vs_pvt");
fd4_ctx->fs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "fs_pvt");
fd4_ctx->vsc_size_mem = fd_bo_new(screen->dev, 0x1000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_size");
fd_context_setup_common_vbos(&fd4_ctx->base);
fd4_query_context_init(pctx);
fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0,
PIPE_USAGE_STREAM, 0);
return pctx;
}
/**
* Create a new texture object, using the given template info.
*/
static struct pipe_resource *
fd_resource_create(struct pipe_screen *pscreen,
const struct pipe_resource *tmpl)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd_resource *rsc = CALLOC_STRUCT(fd_resource);
struct pipe_resource *prsc = &rsc->base.b;
uint32_t flags, size;
DBG("target=%d, format=%s, %ux%u@%u, array_size=%u, last_level=%u, "
"nr_samples=%u, usage=%u, bind=%x, flags=%x",
tmpl->target, util_format_name(tmpl->format),
tmpl->width0, tmpl->height0, tmpl->depth0,
tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
tmpl->usage, tmpl->bind, tmpl->flags);
if (!rsc)
return NULL;
*prsc = *tmpl;
pipe_reference_init(&prsc->reference, 1);
prsc->screen = pscreen;
rsc->base.vtbl = &fd_resource_vtbl;
rsc->pitch = ALIGN(tmpl->width0, 32);
rsc->cpp = util_format_get_blocksize(tmpl->format);
size = rsc->pitch * tmpl->height0 * rsc->cpp;
flags = DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
rsc->bo = fd_bo_new(screen->dev, size, flags);
return prsc;
}
static void
update_vsc_pipe(struct fd_context *ctx)
{
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
int i;
OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x40000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
}
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
}
}
static void
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
uint32_t sz, *bin;
bin = ir3_assemble(v->ir, &v->info, ctx->screen->gpu_id);
sz = v->info.sizedwords * 4;
v->bo = fd_bo_new(ctx->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
memcpy(fd_bo_map(v->bo), bin, sz);
free(bin);
if (ctx->screen->gpu_id >= 400) {
v->instrlen = v->info.sizedwords / (2 * 16);
} else {
v->instrlen = v->info.sizedwords / (2 * 4);
}
/* NOTE: if relative addressing is used, we set constlen in
* the compiler (to worst-case value) since we don't know in
* the assembler what the max addr reg value can be:
*/
v->constlen = MAX2(v->constlen, v->info.max_const + 1);
/* no need to keep the ir around beyond this point: */
ir3_destroy(v->ir);
v->ir = NULL;
}
struct pipe_context *
fd3_context_create(struct pipe_screen *pscreen, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd3_context *fd3_ctx = CALLOC_STRUCT(fd3_context);
struct pipe_context *pctx;
if (!fd3_ctx)
return NULL;
pctx = &fd3_ctx->base.base;
fd3_ctx->base.dev = fd_device_ref(screen->dev);
fd3_ctx->base.screen = fd_screen(pscreen);
pctx->destroy = fd3_context_destroy;
pctx->create_blend_state = fd3_blend_state_create;
pctx->create_rasterizer_state = fd3_rasterizer_state_create;
pctx->create_depth_stencil_alpha_state = fd3_zsa_state_create;
fd3_draw_init(pctx);
fd3_gmem_init(pctx);
fd3_texture_init(pctx);
fd3_prog_init(pctx);
pctx = fd_context_init(&fd3_ctx->base, pscreen, primtypes, priv);
if (!pctx)
return NULL;
util_dynarray_init(&fd3_ctx->rbrc_patches);
fd3_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd3_ctx->fs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd3_ctx->vsc_size_mem = fd_bo_new(screen->dev, 0x1000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
fd3_ctx->solid_vbuf = create_solid_vertexbuf(pctx);
fd3_ctx->blit_texcoord_vbuf = create_blit_texcoord_vertexbuf(pctx);
return pctx;
}
static void
realloc_bo(struct fd_resource *rsc, uint32_t size)
{
struct fd_screen *screen = fd_screen(rsc->base.b.screen);
uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
if (rsc->bo)
fd_bo_del(rsc->bo);
rsc->bo = fd_bo_new(screen->dev, size, flags);
rsc->timestamp = 0;
rsc->dirty = false;
}
static void
realloc_bo(struct fd_resource *rsc, uint32_t size)
{
struct fd_screen *screen = fd_screen(rsc->base.b.screen);
uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
/* if we start using things other than write-combine,
* be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
*/
if (rsc->bo)
fd_bo_del(rsc->bo);
rsc->bo = fd_bo_new(screen->dev, size, flags);
rsc->timestamp = 0;
rsc->dirty = false;
}
static void
assemble_shader(struct pipe_context *pctx, struct fd3_shader_stateobj *so)
{
struct fd_context *ctx = fd_context(pctx);
uint32_t sz, *bin;
bin = ir3_shader_assemble(so->ir, &so->info);
sz = so->info.sizedwords * 4;
so->bo = fd_bo_new(ctx->screen->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
memcpy(fd_bo_map(so->bo), bin, sz);
free(bin);
so->instrlen = so->info.sizedwords / 8;
so->constlen = so->info.max_const + 1;
}
static PixmapPtr create_pixmap(uint32_t w, uint32_t h, uint32_t format)
{
PixmapPtr pix = calloc(1, sizeof(*pix));
int bpp;
if ((format == xRGB) || (format == ARGB)) {
bpp = 32;
} else if (format == A8) {
bpp = 8;
} else {
bpp = 1;
}
pix->width = w;
pix->height = h;
pix->pitch = ALIGN((w * bpp) / 8, 128);
pix->depth = format;
pix->bo = fd_bo_new(dev, pix->pitch * pix->height,
DRM_FREEDRENO_GEM_TYPE_KMEM);
return pix;
}
static void
realloc_bo(struct fd_resource *rsc, uint32_t size)
{
struct fd_screen *screen = fd_screen(rsc->base.b.screen);
uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
/* if we start using things other than write-combine,
* be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
*/
if (rsc->bo)
fd_bo_del(rsc->bo);
rsc->bo = fd_bo_new(screen->dev, size, flags);
rsc->timestamp = 0;
rsc->status = 0;
rsc->pending_ctx = NULL;
list_delinit(&rsc->list);
util_range_set_empty(&rsc->valid_buffer_range);
}
static void
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
uint32_t sz, *bin;
bin = ir3_assemble(v->ir, &v->info);
sz = v->info.sizedwords * 4;
v->bo = fd_bo_new(ctx->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
memcpy(fd_bo_map(v->bo), bin, sz);
free(bin);
v->instrlen = v->info.sizedwords / 8;
/* NOTE: if relative addressing is used, we set constlen in
* the compiler (to worst-case value) since we don't know in
* the assembler what the max addr reg value can be:
*/
v->constlen = MAX2(v->constlen, v->info.max_const + 1);
}
struct fd_bo *
fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
{
struct fd_bo *bo;
if (!is_kgsl_pipe(pipe))
return NULL;
bo = fd_bo_new(pipe->dev, 1, 0);
/* this is fugly, but works around a bug in the kernel..
* priv->memdesc.size never gets set, so getbufinfo ioctl
* thinks the buffer hasn't be allocate and fails
*/
if (bo) {
void *fbmem = drm_mmap(NULL, size, PROT_READ | PROT_WRITE,
MAP_SHARED, fbfd, 0);
struct kgsl_map_user_mem req = {
.memtype = KGSL_USER_MEM_TYPE_ADDR,
.len = size,
.offset = 0,
.hostptr = (unsigned long)fbmem,
};
struct kgsl_bo *kgsl_bo = to_kgsl_bo(bo);
int ret;
ret = ioctl(to_kgsl_pipe(pipe)->fd, IOCTL_KGSL_MAP_USER_MEM, &req);
if (ret) {
ERROR_MSG("mapping user mem failed: %s",
strerror(errno));
goto fail;
}
kgsl_bo->gpuaddr = req.gpuaddr;
bo->map = fbmem;
}
return bo;
fail:
if (bo)
fd_bo_del(bo);
return NULL;
}
drm_private uint32_t kgsl_bo_gpuaddr(struct kgsl_bo *kgsl_bo, uint32_t offset)
{
struct fd_bo *bo = &kgsl_bo->base;
if (!kgsl_bo->gpuaddr) {
struct drm_kgsl_gem_bufinfo req = {
.handle = bo->handle,
};
int ret;
ret = bo_alloc(kgsl_bo);
if (ret) {
return ret;
}
ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
&req, sizeof(req));
if (ret) {
ERROR_MSG("get bufinfo failed: %s", strerror(errno));
return 0;
}
kgsl_bo->gpuaddr = req.gpuaddr[0];
}
return kgsl_bo->gpuaddr + offset;
}
/*
* Super-cheezy way to synchronization between mesa and ddx.. the
* SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
* GET_BUFINFO gives us a way to retrieve it. We use this to stash
* the timestamp of the last ISSUEIBCMDS on the buffer.
*
* To avoid an obscene amount of syscalls, we:
* 1) Only set the timestamp for buffers w/ an flink name, ie.
* only buffers shared across processes. This is enough to
* catch the DRI2 buffers.
* 2) Only set the timestamp for buffers submitted to the 3d ring
* and only check the timestamps on buffers submitted to the
* 2d ring. This should be enough to handle synchronizing of
* presentation blit. We could do synchronization in the other
* direction too, but that would be problematic if we are using
* the 3d ring from DDX, since client side wouldn't know this.
*
* The waiting on timestamp happens before flush, and setting of
* timestamp happens after flush. It is transparent to the user
* of libdrm_freedreno as all the tracking of buffers happens via
* _emit_reloc()..
*/
drm_private void kgsl_bo_set_timestamp(struct kgsl_bo *kgsl_bo,
uint32_t timestamp)
{
struct fd_bo *bo = &kgsl_bo->base;
if (bo->name) {
struct drm_kgsl_gem_active req = {
.handle = bo->handle,
.active = timestamp,
};
int ret;
ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_SET_ACTIVE,
&req, sizeof(req));
if (ret) {
ERROR_MSG("set active failed: %s", strerror(errno));
}
}
}
drm_private uint32_t kgsl_bo_get_timestamp(struct kgsl_bo *kgsl_bo)
{
struct fd_bo *bo = &kgsl_bo->base;
uint32_t timestamp = 0;
if (bo->name) {
struct drm_kgsl_gem_bufinfo req = {
.handle = bo->handle,
};
int ret;
ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
&req, sizeof(req));
if (ret) {
ERROR_MSG("get bufinfo failed: %s", strerror(errno));
return 0;
}
timestamp = req.active;
}
return timestamp;
}
int main(int argc, char *argv[])
{
struct fd_device *dev;
struct fd_pipe *pipe;
struct fd_ringbuffer *ring;
struct fd_bo *bo;
uint32_t i = 0;
uint32_t *ptr;
int fd, ret;
fd = drmOpen("msm", NULL);
if (fd < 0) {
printf("failed to initialize DRM\n");
return fd;
}
dev = fd_device_new(fd);
if (!dev) {
printf("failed to initialize freedreno device\n");
return -1;
}
pipe = fd_pipe_new(dev, FD_PIPE_3D);
if (!pipe) {
printf("failed to initialize freedreno pipe\n");
return -1;
}
ring = fd_ringbuffer_new(pipe, 4096);
if (!ring) {
printf("failed to initialize freedreno ring\n");
return -1;
}
bo = fd_bo_new(dev, 4096, 0);
#define BASE REG_A3XX_GRAS_CL_VPORT_XOFFSET
#define SIZE 6
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG4, 1);
OUT_RING(ring, 0x123);
OUT_PKT0(ring, BASE, SIZE);
for (i = 0; i < SIZE; i++)
OUT_RING(ring, i);
/* this adds the value of CP_SCRATCH_REG4 to 0x111 and writes
* to REG_BASE+2
*/
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
OUT_RING(ring, 0x80000000 | CP_REG(BASE + 2));
OUT_RING(ring, REG_AXXX_CP_SCRATCH_REG4);
OUT_RING(ring, 0x111);
/* read back all the regs: */
for (i = 0; i < SIZE; i++) {
OUT_PKT3(ring, CP_REG_TO_MEM, 2);
OUT_RING(ring, BASE + i);
OUT_RELOCW(ring, bo, i * 4, 0, 0);
}
fd_ringbuffer_flush(ring);
/* and read back the values: */
fd_bo_cpu_prep(bo, pipe, DRM_FREEDRENO_PREP_READ);
ptr = fd_bo_map(bo);
for (i = 0; i < SIZE; i++) {
printf("%02x: %08x\n", i, ptr[i]);
}
fd_bo_cpu_fini(bo);
return 0;
}
static void
fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
{
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct fd4_emit emit = {
.vtx = &fd4_ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
.key = key,
.format = fd4_emit_format(pfb->cbufs[0]),
};
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, 0xff000000 |
A4XX_RB_STENCILREFMASK_STENCILREF(0) |
A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_RING(ring, 0xff000000 |
A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
fd_wfi(ctx, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
0xa); /* XXX */
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
OUT_RING(ring, 0x00000002);
OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
fd4_program_emit(ring, &emit);
fd4_emit_vertex_bufs(ring, &emit);
if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
uint32_t base = depth_base(ctx);
emit_gmem2mem_surf(ctx, base, pfb->zsbuf);
}
if (ctx->resolve & FD_BUFFER_COLOR) {
emit_gmem2mem_surf(ctx, 0, pfb->cbufs[0]);
}
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
}
/* transfer from system memory to gmem */
static void
emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
struct pipe_surface *psurf, uint32_t bin_w)
{
struct fd_ringbuffer *ring = ctx->ring;
emit_mrt(ring, 1, &psurf, &base, bin_w);
fd4_emit_gmem_restore_tex(ring, psurf);
fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
{
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct fd_ringbuffer *ring = ctx->ring;
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct fd4_emit emit = {
.vtx = &fd4_ctx->blit_vbuf_state,
.prog = &ctx->blit_prog[0],
.key = key,
.format = fd4_emit_format(pfb->cbufs[0]),
};
float x0, y0, x1, y1;
unsigned bin_w = tile->bin_w;
unsigned bin_h = tile->bin_h;
unsigned i;
/* write texture coordinates to vertexbuf: */
x0 = ((float)tile->xoff) / ((float)pfb->width);
x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
y0 = ((float)tile->yoff) / ((float)pfb->height);
y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
OUT_PKT3(ring, CP_MEM_WRITE, 5);
OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y0));
OUT_RING(ring, fui(x1));
OUT_RING(ring, fui(y1));
for (i = 0; i < 8; i++) {
OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
A4XX_RB_MRT_CONTROL_B11 |
A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
}
OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
fd4_program_emit(ring, &emit);
fd4_emit_vertex_bufs(ring, &emit);
/* for gmem pitch/base calculations, we need to use the non-
* truncated tile sizes:
*/
bin_w = gmem->bin_w;
bin_h = gmem->bin_h;
if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
0x00010000); /* XXX */
}
static void
patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
util_dynarray_resize(&ctx->draw_patches, 0);
}
static void
patch_rbrc(struct fd_context *ctx, uint32_t val)
{
struct fd4_context *fd4_ctx = fd4_context(ctx);
unsigned i;
for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
*patch->cs = patch->val | val;
}
util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
}
/* for rendering directly to system memory: */
static void
fd4_emit_sysmem_prep(struct fd_context *ctx)
{
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct fd_ringbuffer *ring = ctx->ring;
fd4_emit_restore(ctx);
OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
/* setup scissor/offset for current tile: */
OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
A4XX_RB_BIN_OFFSET_Y(0));
OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
A4XX_RB_MODE_CONTROL_HEIGHT(0) |
0x00c00000); /* XXX */
patch_draws(ctx, IGNORE_VISIBILITY);
patch_rbrc(ctx, 0); // XXX
}
static void
update_vsc_pipe(struct fd_context *ctx)
{
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
int i;
OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x40000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
}
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->pipe[i];
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
}
}
/* before first tile */
static void
fd4_emit_tile_init(struct fd_context *ctx)
{
struct fd_ringbuffer *ring = ctx->ring;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
uint32_t rb_render_control;
fd4_emit_restore(ctx);
OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
0x00010000); /* XXX */
update_vsc_pipe(ctx);
patch_draws(ctx, IGNORE_VISIBILITY);
rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
patch_rbrc(ctx, rb_render_control);
}
/* before mem2gmem */
static void
fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
{
struct fd_ringbuffer *ring = ctx->ring;
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
uint32_t reg;
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
if (pfb->zsbuf) {
reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format));
}
OUT_RING(ring, reg);
if (pfb->zsbuf) {
uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
} else {
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
}
OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
if (pfb->zsbuf) {
OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
fd4_pipe2depth(pfb->zsbuf->format)));
} else {
OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
}
if (ctx->needs_rb_fbd) {
fd_wfi(ctx, ring);
OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
ctx->needs_rb_fbd = false;
}
}
/* before IB to rendering cmds: */
static void
fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
{
struct fd_ringbuffer *ring = ctx->ring;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
uint32_t x1 = tile->xoff;
uint32_t y1 = tile->yoff;
uint32_t x2 = tile->xoff + tile->bin_w - 1;
uint32_t y2 = tile->yoff + tile->bin_h - 1;
OUT_PKT3(ring, CP_SET_BIN, 3);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
/* setup scissor/offset for current tile: */
OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
A4XX_RB_BIN_OFFSET_Y(tile->yoff));
OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
}
void
fd4_gmem_init(struct pipe_context *pctx)
{
struct fd_context *ctx = fd_context(pctx);
ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
ctx->emit_tile_init = fd4_emit_tile_init;
ctx->emit_tile_prep = fd4_emit_tile_prep;
ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
}